Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
Improving charge-collection efficiency of SOI pixel sensors for X-ray astronomy
Introduction
X-ray charge-coupled devices (CCDs) are standard imaging spectrometers widely used in X-ray astronomy because of their fine pixel pitch () and good energy resolution (~130 eV in FWHM at 6 keV) [1], [2], [3]. However, CCDs suffer from problems such as poor time resolution (a few seconds) and a high non-X-ray background especially above 10 keV due to high energy particles in orbit. Thus, we have been developing active pixel sensors, referred to “XRPIX”, for future X-ray astronomy satellites, which allow us to achieve observation with a high-speed readout and a low background.
XRPIX is fabricated using a silicon-on-insulator (SOI) CMOS technology [4] and consists of the following three layers: a low resistivity Si layer for circuits with a thickness of , a high resistivity depleted Si layer for X-ray detection with a thickness up to 500 μm, and a buried oxide (BOX) layer with a thickness of for insulation between the two layers (Fig. 1). Each pixel has a sense node of p+ in the sensor layer connected with the circuit through a via in the BOX layer. A buried p-well (BPW) is implemented around the sense node to suppress the back-gate effect on the circuit and also collects signal charge and transfer it to the sense node because BPWs are implanted so high as to be ohmic [4]. The pixel readout circuit has a trigger capability with time resolution better than 10 μs [5]. The in-pixel trigger circuit also enables event-driven readout, with which we can achieve a low non-X-ray background by using an anti-coincidence technique with surrounding scintillators.
Matsumura et al. [6] found the degradation of the charge-collection efficiency (CCE) at the pixel borders of our second device, XRPIX1b [7], [8]. In this paper, we report on the results of the X-ray beam experiment of XRPIX1b and of investigation using our improved device, XRPIX2b. We discuss the causes of the degradation based on the results and determine its solution.
Section snippets
Experimental setup
We performed measurement of sub-pixel response of XRPIX1b by irradiating with parallel X-ray beams whose diameters are at BL29XUL of SPring-8 [9]. XRPIX1b has a pixel size of 30.6 μm×30.6 μm, a format of 32×32 pixels, and a depletion thickness of 500 μm.
Fig. 2 shows the schematic of the experimental setup, which was previously used for the measurement of a point-spread function of CCD devices [10]. The X-ray beam is shaped with a slit in the optical hutch and a pinhole placed in front
Simulation of electric fields and potentials in XRPIX1b
According to Fig. 5, it seems in general that the detection efficiency outside the BPWs is low in the regions where the circuitry is located, suggesting that the existence of circuitry affects the detection efficiency and the CCE outside the BPWs. In order to confirm it, we ran a 2D simulation of the electric fields and potentials along the cross-section connecting two sense nodes given in Fig. 6(i). We used the semiconductor device simulator HyDeLEOS, which is a part of the TCAD system
Improvement of CCE and detection efficiency
In the study with XRPIX1b, we found that the pixel circuitry has a significant effect on charge collection. It is necessary to solve the problem without increasing the size of BPWs in order to keep low parasitic capacitance of the pixels. Here, we noticed that it would be possible to control the electric fields by arranging the pixel circuitry placement. By a proper layout of the circuitry, we would be able to converge the electric fields into BPWs and detect signal charge without any
Summary
We found that the detection efficiency and the CCE of XRPIX1b degrade at the position under the pixel circuitry with the experiment of the X-ray beams whose diameters are . A 2D simulation shows that the pixel circuitry outside the BPW makes local minimums in the electric potentials in the sensor layer close to the interface with the BOX layer. The degradation of the CCE is explained by the idea that signal charge carried to the local minimum is difficult to escape from there and a
Acknowledgments
We would like to acknowledge the valuable advice and great work by the personnel of LAPIS Semiconductor Co., Ltd. The use of BL29XUL at SPring-8 was supported by RIKEN. We are also grateful to K. Ozaki and T. Wagai for support at SPring-8. This work is supported by JSPS Scientific Research Grant numbers 25109002 (Y.A.), 23340047, 25109004 and 26610047 (T.G.T.), 25109004 and 25870347 (T.T.), and 25109007 (T.H.). This work is also supported by VLSI Design and Education Center (VDEC), the
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2016, Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated EquipmentCitation Excerpt :The XRPIX2bs are the fourth devices in the XRPIX series [19] and are fabricated by LAPIS Semiconductor Co. Ltd., using a 0.2 μm fully depleted SOI CMOS Pixel process. This device is suitable for testing of back-side illumination because it has been well studied [19–21] and includes a large detector (6.0 mm×6.0 mm consisting of 152×152 pixels) compared with the other XRPIXs. Fig. 3 shows the results with the secondary ion mass spectrometry (SIMS) and spreading resistance analysis (SRA) on a device which is made with the same back-side process as the one measured with X-rays.
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2016, Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated EquipmentCitation Excerpt :In stead of the BPW, the middle silicon layer is expected to suppress the back-gate effect because it also works as an electrostatic shield between the sensor and the CMOS circuits. Second, the BPW acts as a part of the sense node and reduction of its size would degrade the charge collection efficiency [14]. Thus, we propose minimizing the BPW size and introducing buried n-wells at the pixel boundaries to optimize the electric field lines collected efficiently toward the BPW and to keep a high charge collection efficiency.