| Project/Area Number |
01044053
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| Research Category |
Grant-in-Aid for Overseas Scientific Survey.
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| Allocation Type | Single-year Grants |
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
ONODA Mahoki Professor, Faculty of Engineering, Tokyo Institute of Technology, 工学部, 教授 (00016312)
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| Co-Investigator(Kenkyū-buntansha) |
HANDAYANI Tj スラバヤ工大, 講師
SAMAUN Samad バンドン工大, 教授
貴家 仁志 (本間 仁志) 東京都立大学, 工学部, 助手 (40157110)
KANEKO Mineo Lecturer, Faculty of Engineering, Tokyo Inst. Tech., 工学部, 講師 (00185935)
KUNIEDA Hiroaki Associate Professor, Faculty of Engineering, Tokyo Inst. Tech., 工学部, 助教授 (50126273)
KIYA Hitoshi Associate, Faculty of Engineering, Tokyo Metropolitan Univ.
SAMADIKUN Samaun Professor, Institute of Technology Bandung ( Indonesia )
TJANDRASA Handayani Lecturer, Institute of Technology Surabaya (Indonesia)
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| Project Period (FY) |
1989
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| Project Status |
Completed (Fiscal Year 1989)
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| Keywords | VLSI ( Very Large Scale Integrated circuits ) / Parallel Signal Processing / Processor Array / Hardware Algorithm |
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| Research Abstract |
Relating to the high-speed sifnal processing hardware design, some new constructions realizing parallel processing using processor arrays are developped at Tokyo Institute of Technology. Hardware design for a new systoric array processing system is obtaind by co-researchers in Institute of Technology Bandung.
Several types of hardware algorithm have been developped by Japanese side researchers and together with Indonesian co-researcher ( Dr. Handayani ) who was invited to TIT by the support of this fund made a development of high-speed signal processing softwares These results have been discussed and reported in Indonesia conference.
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