| Project/Area Number |
01420025
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| Research Category |
Grant-in-Aid for General Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Research Field |
電子材料工学
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
FURUYA Kazuhito Tokyo Inst. Tech., Fac. Eng., Professor, 工学部, 教授 (40092572)
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| Co-Investigator(Kenkyū-buntansha) |
MIYAMOTO Yasuyuki Tokyo Inst. Tech., Fac. Eng., Research Associate, 工学部, 助手 (40209953)
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| Project Period (FY) |
1989 – 1990
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| Project Status |
Completed (Fiscal Year 1990)
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| Budget Amount *help |
¥11,400,000 (Direct Cost: ¥11,400,000)
Fiscal Year 1990: ¥4,900,000 (Direct Cost: ¥4,900,000)
Fiscal Year 1989: ¥6,500,000 (Direct Cost: ¥6,500,000)
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| Keywords | Electron wave phenomenon / Lateral superlattice / Electron beam lithography / Buried growth / GaInAs / InP / OMVPE / Hot electron / Organo-metallic vapor phase epitaxy / 極微細構造 / 電子波 / 横超格子 / 電子波回析 / OMVPE選択成長 / OMVPE埋め込み成長 |
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| Research Abstract |
We have studied wave property of the hot electron in the lateral superlattice theoretically and experimentally to explore the ultra-high speed electron wave device. The following results were obtained.
1) We have investigated about necessary conditions for the observation of the electron wave diffraction phenomenon due to the lateral superlattice. We can avoid the phase randomization of the electron wave, when the wavelength of the hot electron is less than 20nm, the propagation time is less than 0.1ps, the impurity concentration is less than 10^<15>cm^<-3>, and the temperature is below 77K in InGaAs.
2) We have achieved fabrication of the InGaAs/InP lateral superlattice with 70nm-period using the combined technique of the electron beam lithography, the wet chemical etching and OMVPE buried growth. Furthermore, we have examined the regrown interface to reveal the electron accumulation. We have found that this accumulation is reduced by factor more than 10 by the surface treatment with sulfuric ammonium and preheating. We have made it possible to fabricate the lateral superlattice with excellent electric interface properties.
3) We have fabricated the InGaAs/InP hot electron transistor with very high transport efficiency (99.7% across 40nm base, corresponding to the current gain of 400) by the improvement of growth conditions of OMVPE. We have proposed a method for the estimation of the relaxation time. By using this method, the phase relaxation time of the hot electron in InGaAs was estimated as in the order of 0.1ps at 77K.
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