| Project/Area Number |
01420031
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| Research Category |
Grant-in-Aid for General Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Research Field |
計測・制御工学
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| Research Institution | University of Tokyo |
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Principal Investigator |
MORISHITA Iwao Faculty of Engineering, University of Tokyo, Professor, 工学部, 教授 (70010725)
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| Co-Investigator(Kenkyū-buntansha) |
NAGAMATSU Leo Faculty of Engineering, University of Tokyo, Research Associate, 工学部, 助手 (40172556)
DEGUCHI Koichiro Faculty of Engineering, University of Tokyo, Associate Professor, 工学部, 助教授 (30107544)
FUJIMURA Sadao Faulty of Engineering, University of Tokyo, Professor, 工学部, 教授 (30010961)
TAGO Kazuya Faculty of Engineering, University of Tokyo, Research Associate (10188229)
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| Project Period (FY) |
1989 – 1990
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| Project Status |
Completed (Fiscal Year 1990)
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| Budget Amount *help |
¥8,900,000 (Direct Cost: ¥8,900,000)
Fiscal Year 1990: ¥2,300,000 (Direct Cost: ¥2,300,000)
Fiscal Year 1989: ¥6,600,000 (Direct Cost: ¥6,600,000)
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| Keywords | Image Processing / High Speed Image Processing System / Multi Processor / Parallel Processing / Multistage Interconnection Network / Satellite Image / 合成開口レ-ダ |
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| Research Abstract |
A new multi-processor architecture has been developed for high-speed and efficient integrated processing of large amount image data such as satellite images. This system architecture is comprised with newly developed processors which are called pipelined MIMD processors, shared memory and multi-stage interconnection network designed for high speed parallel image processing.
For the total efficient instruction and data flows under memory access delays commonly taking place on a multi-stage interconnection network machine, the new architecture of pipelied MIMD processor is proposed for this system. In this mechanism, multiple independent instruction sequences can run parallel in each single processor under pipelined controls. It enables wide variety of effective parallel image processings from low level to higher levels.
The performance of the system has been evaluated with a variety of simulations and a fully detailed design of the pilot system with this architecture. Their results promises that a high performance processor can be realized in a small sized machine.
With the development of the hardware architecture, algorithms for efficient image processing have been also studied. New image processing techniques for an analysis of under-ground radar images, a shape analysis of planar figures, three dimensional shape recognitions, digital image measurements and so on have been developed.
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