| Project/Area Number |
01460148
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | University of Tokyo |
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Principal Investigator |
DOHI Takeyoshi (1990) Univ. of Tokyo, Faculty of Eng., Professor, 工学部, 教授 (40130299)
芳野 泰成 (1989) 東京大学, 工学部, 助手 (50220702)
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| Co-Investigator(Kenkyū-buntansha) |
OHTA Yuhji Univ. of Tokyo, Faculty of Eng., Research Associate, 工学部, 助手 (50203807)
TOMITA Masahiro Kobe Univ., The Graduate School of Sci. and Tech., Lecturer, 大学院・自然科学研究科, 講師 (60188787)
土肥 健純 東京大学, 工学部, 教授 (40130299)
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| Project Period (FY) |
1989 – 1990
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| Project Status |
Completed (Fiscal Year 1990)
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| Budget Amount *help |
¥4,800,000 (Direct Cost: ¥4,800,000)
Fiscal Year 1990: ¥900,000 (Direct Cost: ¥900,000)
Fiscal Year 1989: ¥3,900,000 (Direct Cost: ¥3,900,000)
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| Keywords | CAD / Printed Wiring Board / Knowledge Acguisition / Element Placement / Routing / Expert System / Bus / Clustering |
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| Research Abstract |
We have developed an automatic layout system, which acquires layout knowledge from skilled designers' drawings and makes use of it to get satisfactory layout result.
Characteristic points in skilled designers' layout strategies are in "clustering" (circuit partitioning), "cluster placement", and bus based methods. Our system acquires knowledge for clustering and cluster placement from skilled designers' layout drawings, and checks contradictions with already fixed rules. In the condition section of each rule, a linear inequality with predictor variables is introduced to judge whether the selected candidates are suitable as an object. Since the coefficients and constants in the linear inequality are determined automatically employing the discriminate function method, conflict resolution between rules from different boards are performed. As a result, the similarity between the system layout result and the manual design has increased according to the number of boards used for knowledge acquisition.
Furthermore, we have developed a hierarchical routing method for bus net routing and for taking influences of all nets including unrouted nets into consideration. For high speed processing of the routing algorithm, we have evaluated several multiprocessing architectures, and the hypercube type architecture including tree network has turned out to be the best for implementation.
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