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Development of High Speed Algorithmic-to-Digital Converters

Research Project

Project/Area Number 01550309
Research Category

Grant-in-Aid for General Scientific Research (C)

Allocation TypeSingle-year Grants
Research Field 電子機器工学
Research InstitutionResearch Institute of Electronics, Shizuoka University

Principal Investigator

WATANABE Kenzo  Shizuoka University, Research Institute of Electronics, Professor, 電子工学研究所, 教授 (70022142)

Project Period (FY) 1989 – 1990
Project Status Completed (Fiscal Year 1990)
Budget Amount *help
¥2,300,000 (Direct Cost: ¥2,300,000)
Fiscal Year 1990: ¥1,500,000 (Direct Cost: ¥1,500,000)
Fiscal Year 1989: ¥800,000 (Direct Cost: ¥800,000)
KeywordsSwitched-capacitor circuits / Unity-gain buffer / Data conversion algorithm / Cyclic A / D converter / Successive-approximation A / CMOS回路
Research Abstract

Cyclic and successive-approximation analog-to-digital(A/D) converters have been developed for high accuracy, high speed data conversion. The former is composed of two 1-b quantizers,each consisting of a unity-gain buffer and a comparator, connected, in closed-loop form. Cicurlating the analog voltage sequence between the two units, the cyclic A/D converter completes the n-b conversion in (n/2+1) clock cycles. The pipeline A/D converter can also be realized by connecting the 1-b quantizers in cascade, to update the n-b parallel output every clock cycle.
The successive-approximation A/D converter of a comparator and a digitalto-analog (D/A) converter. For easy implementation, a serial D/A converter is developed based on a new algorithm to start a conversion with the most significant bit. An input analog voltage is converted into its digital equivalent by being compared successively with the quantized threshold voltage sequence generated by the D/A converter. Thus, it requires n clock cycl … More es for n-b conversion.
In both converters, switched-capacitor techniques are used for executing the conversion algorithms, and thus they lend themselves to monolithic implementations using CMOS process. Spice simulations assuming 3 mum CMOS process show that conversion accuracy and speed higher than 8-b and 15 Mbps, respectively, can be expected from monolithic implementation of the cyclic A/D converter. A power consumption is estimated to be 50 mW for the 8-b pipeline converter. A conversion accuracy higher than 11-b is possible with monolithic implementation of the successive-approximation A/D converter.
The principles of operation and accuracy estimates have been confirmed by prototype converters built using discrete components. The cyclic A/D converter has also been fabricated using bipolar analog macro cells. The conversion accuracy at the conversion speed 1 Mbps was 7-b. This was attributed to alarge droop in the sample/hold stage. Therefore, the accuracy can be much improved by using the buffer with high input impedance.
The A/D converters developed here feature small device counts integrable onto small chip areas using a CMOS process, and thus are best suited for the front ends of hybrid analog and digital ASIC's. Less

Report

(3 results)
  • 1990 Annual Research Report   Final Research Report Summary
  • 1989 Annual Research Report
  • Research Products

    (19 results)

All Other

All Publications (19 results)

  • [Publications] S.Ogawa,K.Kondoh,and K.Watanabe: "A bufferーbased algorithmic analogーtoーdigital converter" Proc.Int.Symp.Circuits and Systems. 276-279 (1989)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] S.Ogawa and K.Watanabe: "An algorithmic analogーtoーdigital converter using unityーgain buffers" Proc.IEEE Instrum.Meas.Tech.Conf.227-231 (1990)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] K.Watanabe,G.C.Temes,and T.Tagami: "A new algorithm for cyclic and pipeline data conversion" IEEE Trans.Circuits and Systems. 37. 249-253 (1990)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] 小川 覚美,渡辺 健藏: "単位利得バッファを用いたアルゴリズミックAD変換器" 静岡大学電子工学研究所研究報告. 25. 21-30 (1990)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] S.Ogawa and K.Watanabe: "An algorithmic analogーtoーdigital converter using unityーgain buffers" IEEE Trans.Instrum.Meas.39. 886-889 (1990)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] 小川 覚美,渡辺 健藏: "スイッチドキャパシタ逐次比較型AD変換器とそのキャパシタンスメ-タへの応用" 静岡大学電子工学研究所研究報告. 25.

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] OGAWA, S. KONDOH, K. and WATANABE, K.: "A buffer-based algorithmic analog-to-digital converter" Proc. Int. Symp. Circuits and Systems. 276-279 (1989)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] OGAWA, S. and WATANABE, K.: "An algorithmic analog-to-digital converter using unity-gain buffers" Proc. IEEE Instrum. Meas. Tech. Conf.227-231 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] WATANABE, K. G. C. TEMES, and TAGAMI, T.: "A new algorithm for cyclic and pipeline data conversion" IEEE Trans. Circuits and Systems. vol. 37. 249-253 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] OGAWA Satomi and WATANABE Kenzo: "Algorithmic analog-to-digital converters based on unity-gain buffers (in Japanese)" Bullentin of the Research Inst. Electronics. vol. 25. 21-30 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] OGAWA, S. and WATANABE, K.: "An algorithmic analog-to-digital converter using unity-gain buffers" IEEE Trans. Instrum. Meas.vol. 39. 886-889 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] OGAWA Satomi and WATANABE Kenzo: "A switched-capacitor successive-approximation AD converter and its application to capacitance measurement (in Japanese)" Bulletin of the Research Inst. Electronics, Shizuoka University. vol. 25.

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] OGAWA, S. and WATANABE, K.: "A switched-capacitor successive-approximation analog-to-digital converter" IEEE Int. Symp. Circuits and Systems.

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1990 Final Research Report Summary
  • [Publications] 小川 覚美,渡辺 健藏: "単位利得バッファを用いたアルゴリズミックAD変換器" 静岡大学電子工学研究所研究報告. 25. 21-30 (1990)

    • Related Report
      1990 Annual Research Report
  • [Publications] Kenzo Watanabe,Satomi Ogawa: "An algorithmic AnaloyーtoーDigital Converter using UnityーGain Buffers" IEEE Transactions on Instrumentation and Measurement. 39. 886-889 (1990)

    • Related Report
      1990 Annual Research Report
  • [Publications] 小川 覚美,渡辺 健藏: "スイッチドキャパシタ逐次比較型AD変換器とそのキャパシタンスメ-タへの応用" 静岡大学電子工学研究所研究報告. 25. (1991)

    • Related Report
      1990 Annual Research Report
  • [Publications] Satomi Ogawa and Kenzo Watanabe: "A SwitchedーCapacitor SuccessiveーApproximation AnalogーtoーDigital Converter" Proc.International Symposium on Circuits and Systems. (1991)

    • Related Report
      1990 Annual Research Report
  • [Publications] Satomi Ogawa,Kazuyuki Kondoh,Kenzo Watanabe: "A buffer-based algorithmic analog-to-digital conbverter" Proceedings of 1989 IEEE International Symposium on Circuits and Systems. 276-279 (1989)

    • Related Report
      1989 Annual Research Report
  • [Publications] Satomi Ogawa and Kenzo Watanabe: "An algorithmic analog-to-digital converter usoing unitygain buffers" Conference Record of IEEE Instrumentation and Measurement Technology Conference. 227-231 (1990)

    • Related Report
      1989 Annual Research Report

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Published: 1989-04-01   Modified: 2016-04-21  

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