| Budget Amount *help |
¥2,300,000 (Direct Cost: ¥2,300,000)
Fiscal Year 1990: ¥1,500,000 (Direct Cost: ¥1,500,000)
Fiscal Year 1989: ¥800,000 (Direct Cost: ¥800,000)
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| Research Abstract |
Cyclic and successive-approximation analog-to-digital(A/D) converters have been developed for high accuracy, high speed data conversion. The former is composed of two 1-b quantizers,each consisting of a unity-gain buffer and a comparator, connected, in closed-loop form. Cicurlating the analog voltage sequence between the two units, the cyclic A/D converter completes the n-b conversion in (n/2+1) clock cycles. The pipeline A/D converter can also be realized by connecting the 1-b quantizers in cascade, to update the n-b parallel output every clock cycle.
The successive-approximation A/D converter of a comparator and a digitalto-analog (D/A) converter. For easy implementation, a serial D/A converter is developed based on a new algorithm to start a conversion with the most significant bit. An input analog voltage is converted into its digital equivalent by being compared successively with the quantized threshold voltage sequence generated by the D/A converter. Thus, it requires n clock cycl
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es for n-b conversion.
In both converters, switched-capacitor techniques are used for executing the conversion algorithms, and thus they lend themselves to monolithic implementations using CMOS process. Spice simulations assuming 3 mum CMOS process show that conversion accuracy and speed higher than 8-b and 15 Mbps, respectively, can be expected from monolithic implementation of the cyclic A/D converter. A power consumption is estimated to be 50 mW for the 8-b pipeline converter. A conversion accuracy higher than 11-b is possible with monolithic implementation of the successive-approximation A/D converter.
The principles of operation and accuracy estimates have been confirmed by prototype converters built using discrete components. The cyclic A/D converter has also been fabricated using bipolar analog macro cells. The conversion accuracy at the conversion speed 1 Mbps was 7-b. This was attributed to alarge droop in the sample/hold stage. Therefore, the accuracy can be much improved by using the buffer with high input impedance.
The A/D converters developed here feature small device counts integrable onto small chip areas using a CMOS process, and thus are best suited for the front ends of hybrid analog and digital ASIC's. Less
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