| Project/Area Number |
01850072
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| Research Category |
Grant-in-Aid for Developmental Scientific Research
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | University of Tsukuba |
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Principal Investigator |
ITANO Kozo Univ. Tsukuba, Inst. of Infor. Sci. and Electronics, Assistant Professor, 電子情報工学系, 助教授 (20114035)
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| Co-Investigator(Kenkyū-buntansha) |
KIYOKI Yasushi Univ. Tsukuba, Inst. of Infor. Sci. and Electronics, Assistant Professor, 電子情報工学系, 助教授 (10169956)
IDA Tetsuo Univ. Tsukuba, Inst. of Infor. Sci. and Electronics, Assistant Professor, 電子情報工学系, 助教授 (70100047)
WADA Koichi Univ. Tsukuba, Inst. of Infor. Sci. and Electronics, Assistant Professor, 電子情報工学系, 助教授 (30175145)
佐々 政孝 筑波大学, 電子情報工学系, 助教授 (20016182)
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| Project Period (FY) |
1989 – 1991
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| Project Status |
Completed (Fiscal Year 1991)
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| Budget Amount *help |
¥18,600,000 (Direct Cost: ¥18,600,000)
Fiscal Year 1991: ¥3,700,000 (Direct Cost: ¥3,700,000)
Fiscal Year 1990: ¥7,200,000 (Direct Cost: ¥7,200,000)
Fiscal Year 1989: ¥7,700,000 (Direct Cost: ¥7,700,000)
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| Keywords | computer architecture / parallel processing architecture / polyprocessor system / parallel processing language / parallel processing algorithm |
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| Research Abstract |
The investigaters have designed and built a multi-transputer system as the basis of parallel processing computing environment with a message driven computing model, in order to establish the effective parallel programming technique for non-numeric computing. A prototype of a parallel processing language has also been implemented to control the processors. Sine a simple message driven synchronization mechanism cannot control parallel processes elaborately, both lasy and eager evaluations were used for the execution control. Actual hardware prototype consists of 64 transputers which are connected to each other. A shared memory machine was also designed and evaluated by the simulation.
The sample applications were chosen from the non-numric processing such as hardware logic simulaton and semantic analysis of a compiler. For the logic simulation, each logic component is abstracted as a basic primitive process, and the whole logic system is described as a collection of processes which are connected by the message, then the processes are distributed among the transputers. For the semantic analysis of a compiler, the whole semantic analysis process is separated into small pieces of analysis relating to the corresponding syntactical units, then semantic analysis processes are generated dynamically. The generated processes are connected to each other by streams to control the execution. These sample applications were actually implemented and executed for the evaluation.
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