| Project/Area Number |
01850076
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| Research Category |
Grant-in-Aid for Developmental Scientific Research
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | Kyoto University |
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Principal Investigator |
TAMARU Keikichi Kyoto Univ., Faculty of Engineering, Professor, 工学部, 教授 (10127102)
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| Co-Investigator(Kenkyū-buntansha) |
SHINPO Shintaro Mitsubishi Electric Corp., ASIC Design Eng. Center, Manager, カスタムLSI設計技術開発センター, グループマネージャ
ONODERA Hidetoshi Kyoto Univ., Faculty of Engineering, Assoc. Professor, 工学部, 助教授 (80160927)
NAKAJIMA Masamitsu Kyoto Univ., Faculty of Engineering, Assoc. Professor, 工学部, 助教授 (60025939)
安浦 寛人 京都大学, 工学部, 助教授 (80135540)
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| Project Period (FY) |
1989 – 1991
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| Project Status |
Completed (Fiscal Year 1991)
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| Budget Amount *help |
¥14,800,000 (Direct Cost: ¥14,800,000)
Fiscal Year 1991: ¥400,000 (Direct Cost: ¥400,000)
Fiscal Year 1990: ¥4,000,000 (Direct Cost: ¥4,000,000)
Fiscal Year 1989: ¥10,400,000 (Direct Cost: ¥10,400,000)
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| Keywords | Integrated Analog-Digital CAD System / Symbolic Layout / Automatic Layout / Logic Synthesis / Circuit Synthesis / LSI CAD / Module Generator / CAD Framework / アナログ-ディジタル統合CADシステム / シンポリックレイアウト / コンパクション / アナログ回路自動合成 / 自動論理合成 / CADデ-タベ-ス / アナログLSI / ディジタルLSI / アナログ-ディジタル混載LSI / アナログ-ディジタル統合CAD |
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| Research Abstract |
The purpose of this research project is the development of an integrated Analog-Digital CAD system that supports circuit and layout design for Analog and mixed Analog-Digital LSIS. The results of the project are summarized as follows.
1. We have developed a symbolic layout system. The system allows a designer to define new layout patterns of any devices which are tailored according to his need. Newly established compaction algorithm enables the system to compact Analog layout under symmetry constraints.
2. We have developed a system for module generator development. A method for generating layout description from a graphically designed layout has been devised. With the use of the system, a designer can develop a module generator using a graphic editor, which is more user-friendly than conventional programming.
3. We have established an automatic placement method for building blocks and analog components. The placement algorithm is a branch-and-bound search for an optimal solution from all the possible placements.
4. We have developed an automatic design system for CMOS operational amplifier-amps. A knowledge-based process followed by a numerical optimization searches for a good design effectively in a vast solution space. During device sizing, layout information are back-annotated "on the fly", thus circuit performance is optimized considering the effect of layout parasitics precisely.
5. We have developed a layout-driven logic synthesis system. Terminal positions of logic gates are taken into account in a logic restructuring process, which consideration will reduce interconnection length of a final circuit. The output of the system is a standard cell layout.
6. We have considered a method of evaluation for CAD tools, and proposed a comprehensive set of benchmarks which is applicable to CAD tools for any design levels.
In this project we mainly focused on a synthesis phase of LSI design. Our further research will include verification and test of LSIs.
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