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Development of an Integrated Analog-Digital CAD System

Research Project

Project/Area Number 01850076
Research Category

Grant-in-Aid for Developmental Scientific Research

Allocation TypeSingle-year Grants
Research Field 計算機工学
Research InstitutionKyoto University

Principal Investigator

TAMARU Keikichi  Kyoto Univ., Faculty of Engineering, Professor, 工学部, 教授 (10127102)

Co-Investigator(Kenkyū-buntansha) SHINPO Shintaro  Mitsubishi Electric Corp., ASIC Design Eng. Center, Manager, カスタムLSI設計技術開発センター, グループマネージャ
ONODERA Hidetoshi  Kyoto Univ., Faculty of Engineering, Assoc. Professor, 工学部, 助教授 (80160927)
NAKAJIMA Masamitsu  Kyoto Univ., Faculty of Engineering, Assoc. Professor, 工学部, 助教授 (60025939)
安浦 寛人  京都大学, 工学部, 助教授 (80135540)
Project Period (FY) 1989 – 1991
Project Status Completed (Fiscal Year 1991)
Budget Amount *help
¥14,800,000 (Direct Cost: ¥14,800,000)
Fiscal Year 1991: ¥400,000 (Direct Cost: ¥400,000)
Fiscal Year 1990: ¥4,000,000 (Direct Cost: ¥4,000,000)
Fiscal Year 1989: ¥10,400,000 (Direct Cost: ¥10,400,000)
KeywordsIntegrated Analog-Digital CAD System / Symbolic Layout / Automatic Layout / Logic Synthesis / Circuit Synthesis / LSI CAD / Module Generator / CAD Framework / アナログ-ディジタル統合CADシステム / シンポリックレイアウト / コンパクション / アナログ回路自動合成 / 自動論理合成 / CADデ-タベ-ス / アナログLSI / ディジタルLSI / アナログ-ディジタル混載LSI / アナログ-ディジタル統合CAD
Research Abstract

The purpose of this research project is the development of an integrated Analog-Digital CAD system that supports circuit and layout design for Analog and mixed Analog-Digital LSIS. The results of the project are summarized as follows.
1. We have developed a symbolic layout system. The system allows a designer to define new layout patterns of any devices which are tailored according to his need. Newly established compaction algorithm enables the system to compact Analog layout under symmetry constraints.
2. We have developed a system for module generator development. A method for generating layout description from a graphically designed layout has been devised. With the use of the system, a designer can develop a module generator using a graphic editor, which is more user-friendly than conventional programming.
3. We have established an automatic placement method for building blocks and analog components. The placement algorithm is a branch-and-bound search for an optimal solution from all the possible placements.
4. We have developed an automatic design system for CMOS operational amplifier-amps. A knowledge-based process followed by a numerical optimization searches for a good design effectively in a vast solution space. During device sizing, layout information are back-annotated "on the fly", thus circuit performance is optimized considering the effect of layout parasitics precisely.
5. We have developed a layout-driven logic synthesis system. Terminal positions of logic gates are taken into account in a logic restructuring process, which consideration will reduce interconnection length of a final circuit. The output of the system is a standard cell layout.
6. We have considered a method of evaluation for CAD tools, and proposed a comprehensive set of benchmarks which is applicable to CAD tools for any design levels.
In this project we mainly focused on a synthesis phase of LSI design. Our further research will include verification and test of LSIs.

Report

(4 results)
  • 1991 Annual Research Report   Final Research Report Summary
  • 1990 Annual Research Report
  • 1989 Annual Research Report
  • Research Products

    (47 results)

All Other

All Publications (47 results)

  • [Publications] Hidetoshi Onodera: "Operational Amplifier Compilation with Performance Optimization" Proc.of the IEEE 1989 Custom Integrated Circuits Conference. 17.4.1-17.4.6 (1989)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] 坂本 守: "シフトコンパクションーシンボリックレイアウトの擬2次元的コンパクション手法ー" 電子情報通信学会論文誌A. J72ーANo.8. 1277-1286 (1989)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] Ryosuke Okuda: "An Efficient Algorithm for Layout Compaction Problem with Symmetry Constraints" Proc.of the 1989 IEEE International conference on Computer-Aided Design. 148-151 (1989)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] 小野寺 秀俊: "OAC:CMOCオペアンプ自動設計システムーシステム概要と評価ー" 電子情報通信学会論文誌A. J73ーANo.1. 67-76 (1990)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] 奥田 亮輔: "対称性保持の制約を扱えるレイアウトコンパクションアルゴリズム" 電子情報通信学会論文誌A. J73ーANo.3. 536-543 (1990)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] Hidetoshi Onodera: "Branch-and Bound Placement for Building Block Layout" Proc.of 1990 International Workshop on Layout Synthesis. (1990)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] Hidetoshi Onodera: "Operational-Amplifier Compilation with Performance Optimization" IEEE J.of Solid-State Circuits. 25,No.2. 466-473 (1990)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] Hiroto Yasuura: "Semantic Gap between Hardware Design Languages and Simulators" Proc.of the Synthesis and Simulation Meeting and International Interchange. 165-172 (1990)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] Masahiko Ohmura: "Extraction of Arithmetic Functions from Combinational Circuits" Proc.of the Synthesis and Simulation Meeting and International Interchange. 40-47 (1990)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] 安浦 寛人: "論理合成問題における最適化" Proc.of the 2nd RAMP Symp.89-97 (1990)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] Masahiko Ohmura: "Extraction of Functional Information from Combinational Circuits" Proc.of the 1990 IEEE International Conference on Computer-Aided Design. 176-179 (1990)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] 大村 昌彦: "組合せ回路の機能情報抽出" 電子情報通信学会論文誌A. J74ーANo.2. 247-255 (1991)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] 音羽 克則: "CMOSオペアンプ自動設計システムOACにおける自動回路設計手法ー回路構成と素子概略値の決定ー" 電子情報通信学会論文誌A. J74ーANo.2. 277-286 (1991)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] 小野寺 秀俊: "アナログ回路の合成と最適化" 電子情報通信学会論文誌A. J74ーANo.2. 179-186 (1991)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] 淡海 功二: "UDL/Iのセマンティクス定義に基づく可変精度シミュレ-タの試作" Proc.of the 4th Karuizawa Workshop on Circuits and Systems. 57-62 (1991)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] 大村 昌彦: "同期式順序回路の機能情報抽出" Proc of the 4th Karuizawa Workshop on Circuits and Systems. 52-56 (1991)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] Hidetoshi Onodera: "Branch-and-Bound Placement for Building Block Layout" Proc.of 28th ACM/IEEE Design Automation Conference. 433-439 (1991)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] H. Onodera, H. kanbara and K. Tamaru: "Operational Amplifier compilation with Performance Optimization" Proc. 1989 CICC. 17.4.1-17.4.6 (1989)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] M. Sakamoto, H. Onodera, and K. Tamaru: "Shiftcompaction -Quasi Two-Dimensional Compaction Method for Symbolic Layout-" Trans. IEICE Japan. J72-A. 1277-1286 (1989)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] R. Okuda, T. Sato, H. Onodera, and K. Tamaru: "An Efficient Algorithm for Layout Compaction Problem with Symmetry Constraints" Proc. 1989 ICCAD. 148-151 (1989)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] H. Onodera, K. Kanbara, and K. Tamaru: "OCA : CMOS Operational Amplifier Compiler -Overview of the System and Its Evaluation-" Trans. IEICE Japan. J73-A. 67-76 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] R. Okuda, and T. Sato, H. Onodera, and K. Tamraru: "An Algorithm for Layout Compaction Problem with Symmetry Constraints" Trans. IEICE Japan. J73-A. 536-543 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] H. Onodera, Y. Taniguchi and K. Tamaru: "Branch-and Bound Placement for Building Block Layout" Proc. of 1990 International Workshop on Layout Synthesis. (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] H. Onodera, H. Kanbara and K. Tamaru: "Operational -Amplifier Compilation with Performance Optimization" IEEE J. of Solid-State Circuits. 25. 466-473 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] H. Yasuura, K. Tankai and K. Tamaru: "Semantic Gap between Hardware Design Languages and Simulators" Proc. 1990 SASIMI. 165-172 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] M. Ohmura, H. Yasuura and K. Tamaru: "Extraction of Arithmetic Functions from Combinational Circuits" Proc. 1990 SASIMI. 40-47 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] Hiroto Yasuura: "Optimization in Logic Synthesis Problem" Proc. of the 2nd RAMP Symp.89-97 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] M. Ohmura, H. Yasuura and K. Tamaru: "Extraction of Functional Information from Combinational Circuits" Proc. 1990 ICCAD. 176-179 (1990)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] M. Ohmura, H. Yasuura, and K. Tamaru: "Functional Information Extraction from Combinational Circuits" Trans. IEICE Japan. J74-A. 247-255 (1991)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] K. Otoba, T. Yasuda, H. Onodera, and K. Tamaru: "Circuit Design Method in the CMOS Operational Amplifier Compiler OAC -Determination of Circuit Topology and Rough Device Size-" Trans. IEICE Japan. J74-A. 277-286 (1991)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] Hidetoshi Onodera: "Synthesis and Optimization of Analog Circuits" Trans. IEICE Japan. J74-A. 179-186 (1991)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] K. Tankai, F. Ohtala. H. Yasuura, and K. Tamaru: "Development of a Variable Accuracy Logic Simulator Based on Semantic Definition of UDL/I" Proc. 4th Karuizawa Workshop on CAS. 57-62 (1991)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] M. Ohmura, H. Yasuura, and K. Tamaru: "Extraction of Functional Information from Synchronous Sequential Circuits" Proc. 4th Karuizawa Workshop on CAS. 52-56 (1991)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] H. Onodera, Y. Taniguchi and K. Tamaru: "Branch-and-Bound Placement for Building Block Layout" Proc. of 28th DAC. 433-439 (1991)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1991 Final Research Report Summary
  • [Publications] 淡海 功二: "UDL/Iのセマンティクス定義に基づく可変精度シミュレ-タの試作" Proc.of the 4th Karuizawa Workshop on Circuits and Systems. 57-62 (1991)

    • Related Report
      1991 Annual Research Report
  • [Publications] 大村 昌彦: "同期式順序回路の機能情報抽出" Proc.of the 4th Karuizawa Workshop on Circuits and Systems. 52-56 (1991)

    • Related Report
      1991 Annual Research Report
  • [Publications] Hidetoshi Onodera: "Branch-and-Bound Placement for Building Block Layout" Proc.of 28th ACM/IEEE Design Automation Conference. 433-439 (1991)

    • Related Report
      1991 Annual Research Report
  • [Publications] Hidetoshi Onodera: "Analog Circuit PlacementーBranch-and-Bound Placement with Shape Optimizationー" Proc.1992 CICC.

    • Related Report
      1991 Annual Research Report
  • [Publications] 奥田 亮輔: "対称性保持の制約を扱えるレイアウトコンパクションアルゴリズム" 電子情報通信学会 論文誌. J73ーAー3. 536-543 (1990)

    • Related Report
      1990 Annual Research Report
  • [Publications] Hidetoshi Onodera: "OperationalーAmplifier Compilation with Performance Optimization" IEEE Journal of SolidーState Circuits. 25ー2. 466-473 (1990)

    • Related Report
      1990 Annual Research Report
  • [Publications] Hiroto Yasuura: "Formal Semantics of UDL/I and Its Application to CAD/DA Tools" 1990 IEEE International Conference on Computer Design:VLSI in Computers & Processors ICCD '90. 90-94 (1990)

    • Related Report
      1990 Annual Research Report
  • [Publications] 小野寺 秀俊: "アナログ回路の合成と最適化" 電子情報通信学会 論文誌. J74ーAー2. 179-186 (1991)

    • Related Report
      1990 Annual Research Report
  • [Publications] 音羽 克則: "CMOSオペアンプ自動設計システムOACにおける自動回路設計手法 ー回路構成と素子概略値の決定ー" 電子情報通信学会 論文誌. J74ーAー2. 277-286 (1991)

    • Related Report
      1990 Annual Research Report
  • [Publications] H.Onodera: "Operational Amplifier Compilation with Performance Optimization" Proc.1989 IEEE Custum Integrated Circuits Conference. 17.4.1-17.4.6 (1989)

    • Related Report
      1989 Annual Research Report
  • [Publications] 小野寺秀俊: "OAC:CMOSオペアンプ自動設計システム-システム概要と評価-" 電子情報通信学会論文誌 A. JT3-A. 67-76 (1990)

    • Related Report
      1989 Annual Research Report
  • [Publications] R.Okuda: "An Efficient Algorithm for Layout Compaction Problem with Symmetry Constraints" Proc.1989IEEE International Conference on Computer-Aided Design. 148-151 (1989)

    • Related Report
      1989 Annual Research Report
  • [Publications] 奥田亮輔: "対称性保持の制約を扱えるレイアウトコンパクションアルゴリズム" 電子情報通信学会論文誌A. JT3-A. (1990)

    • Related Report
      1989 Annual Research Report

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Published: 1989-04-01   Modified: 2019-02-15  

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