| Project/Area Number |
01850085
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| Research Category |
Grant-in-Aid for Developmental Scientific Research (B).
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| Allocation Type | Single-year Grants |
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| Research Field |
計測・制御工学
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| Research Institution | Tohoku University |
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Principal Investigator |
KAMEYAMA Michitaka Tohoku University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (70124568)
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| Co-Investigator(Kenkyū-buntansha) |
TOMABECHI Nobuhiro Hachinohe Institute of Technology, Faculty of Engineering, Professor, 工学部, 教授 (70048180)
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| Project Period (FY) |
1989 – 1990
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| Project Status |
Completed (Fiscal Year 1990)
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| Budget Amount *help |
¥2,400,000 (Direct Cost: ¥2,400,000)
Fiscal Year 1990: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 1989: ¥1,300,000 (Direct Cost: ¥1,300,000)
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| Keywords | Symmetric Residue Number System / Multiple-Valued Current-Mode Logic / Signed-Digit Arithmetic Circuit / Highly-Parallel Multiply Adder / Current-Mode CMOS Integrated Circuit / Residue Arithmetic VLSI / VLSI / 剰余数演算回路 / 高並列演算 / 多値演算回路 / 双方向電流モ-ドCMOS |
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| Research Abstract |
This research discusses the implementation of a new residue arithmetic integrated circuit based on multiple-valued coding and multiple-valued bidirectional current-mode MOS technology. A new multiple-valued coded residue digit representation is introduced based on the pseudo-primitive root. With this coding, mod m multiplication and mod m addition can be executed using only shift and radix-5 signed-digit arithmetic operations, respectively. Furthermore, mod m multiplication by a constant coefficient can be performed simply by exchanging wire connections.
Multiple-valued bidirectional current-mode MOS technology is employed to implement the residue arithmetic circuit. In order to confirm the principle operations, the mod 7 three-operand multiply adder composed of 190 transistors has been designed and fabricated in 10-um CMOS design rule. The arithmetic circuit has a regular array structure which offers the potential for compact VLSI implementation.
Although residue arithmetic operations are restricted on integer arithmetic, the above high performance can hardly be achieved thorough the use of conventional binary arithmetic circuit. This highly parallel residue arithmetic chip will be of great use in many real-time applications such as robot systems.
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