| Project/Area Number |
02452156
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
NANYA Takashi Tokyo Institute of Technology Faculty of Engineering, Professor, 工学部, 教授 (80143684)
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| Co-Investigator(Kenkyū-buntansha) |
TONEDA Tomohiro Tokyo Institute of Technology Faculty of Engineering Associate Professor, 工学部, 助教授 (30182851)
FUJIWARA Eiji Tokyo Institute of Technology Faculty of Engineering, Professor, 工学部, 教授 (20211526)
TOHMA Yoshihiro Tokyo Institute of Technology Faculty of Engineering, Professor, 工学部, 教授 (50016317)
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| Project Period (FY) |
1990 – 1991
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| Project Status |
Completed (Fiscal Year 1991)
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| Budget Amount *help |
¥6,000,000 (Direct Cost: ¥6,000,000)
Fiscal Year 1991: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 1990: ¥5,500,000 (Direct Cost: ¥5,500,000)
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| Keywords | Fault-tolerance / Self-checking / Processor Organization / Logic Circuits / Logic Synthesis / 論理式除算 |
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| Research Abstract |
Self-checking circuit design has been widely recognized as an essential technique for concurrent error detection in fault-tolerant systems. Important concepts which have been well established include : totally selfchecking(TSC)circuits which are defined to be both fault-secure(FS)and self-testing(ST), strongly faultsecure(SFS)circuits, code-disjoint(CD)circuits which include checkers as a special class, and strongly codedisjoint(SCD)circuits. SFS circuits achieve the TSC goal of producing a non-codeword as the first erroneous output due to a fault. SCD circuits always map non-codeword inputs to non-codeword outputs even in the presence of faults so long as the faults remain undetectable. Thus, the circuit structure which consists of an SFS functional circuit with its output monitored by an SCD checker effectively provides the largest class of self-checking circuits that achieve the TSC goal. Two or more functional circuits may be interconnected to compose a larger logic network. If a c
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omponent functional circuit embedded in the network is not only SFS but also SCD, the input of the component circuit need not be monitored by an SCD checker in order for the entire logic network to achieve the TSC goal. In this research, two important design techniques have been established for the realization of a large logic network that effectively achieves the TSC goal. First, a systematic design method is presented for SFS and SCD sequential circuits with the intensive use of highly structured logic arrays. Second, a remapping technique is presented for embedded logic functions of both combinational and sequential circuits which are interconnected with each other to compose a larger logic network. The proposed technique allows the embedded input interface of each component functional circuits to be fully exercised in normal operation so that the entire logic network proves to be SFS and SCD. Based on these design techniques, a prototype system of an automatic synthesizer for self-checking logic networks has been implemented, and shown to be useful for the automatic synthesis of self-checking processors. Less
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