| Project/Area Number |
02452165
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | Osaka University |
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Principal Investigator |
KINOSHITA Kozo Osaka University, Professor, 工学部, 教授 (00028995)
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| Co-Investigator(Kenkyū-buntansha) |
YASUI Hiroshi Osaka Sangyo University, Professor (1990), 工学部, 教授 (60029014)
TAKAMATSU Yuzo Ehime University, Professor, 工学部, 教授 (80039255)
ITAZAKI Noriyoshi Osaka University, Assistant Professor, 工学部, 助手 (90223073)
KOMATSU Masaharu Osaka University, Associate Professor (1990-1991), 工学部, 助教授 (90116583)
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| Project Period (FY) |
1990 – 1992
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| Project Status |
Completed (Fiscal Year 1992)
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| Budget Amount *help |
¥6,300,000 (Direct Cost: ¥6,300,000)
Fiscal Year 1992: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 1991: ¥1,000,000 (Direct Cost: ¥1,000,000)
Fiscal Year 1990: ¥4,600,000 (Direct Cost: ¥4,600,000)
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| Keywords | Testable Design / Fault Diagnosis / Electron Beam Testing / Highly Observable Testing / LST Testing / 論理回路 / 電子ビ-ムテスト / 診断容易化設計 / テストパタ-ン生成 |
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| Research Abstract |
The major results obtained from this research are as follows: 1)Testable design of logic circuits under the highly observable condition As testable logic circuits under the highly observable condition, the concept of K-UC NAND circuits has been proposed, and as its extension, the concept of k-UCP circuits has been proposed. Stuck-at faults and stuck-open faults are considered as fault models and it has been shown that the numbers of necessary test patterns for the two fault models are k + 1 and k (k + 1) + 1, respectively. Furthermore, the idea has been extended to the testing of sequential circuits under the highly observable condition and the corresponding testing method has been proposed.
2)Test pattern generation under the highly observable condition Under the highly observable condition, it is assumed that the internal signal lines in a circuit are observable. Thus, it is unnecessary to propagate the effect of faults to primary output lines. As a result, the number of primary input
… More
lines needed to be assigned logic values for testing a fault becomes small and the generation of the test patterns detecting multiple faults at the same time becomes easy. Furthermore, this method has been applied to the test pattern generation of sequential circuits and it has been shown that the numbers of test patterns are considerably smaller than previous methods.
3)Fault diagnosis under the highly observable condition In order to locate a fault, it is necessary to reduce the size of a fault table to a practical size. In this method, the number of possible faults is reduced by analyzing the response for applying test vector pairs and the number of possible faults positions is reduced by analyzing the responses for applying test vector pairs and the number of repetitively. This method can be used for ordinary combinational circuits and allows the existence of multiple faults as target faults. Besides, this method does not make direct use of a fault table, thus has the advantage of using only a relatively small memory for computation. As the extension of fault diagnosis methods by using an electron beam tester, a method for guided-probe fault diagnosis has been proposed and its effectiveness has been verified by making experiments on benchmark circuits. Less
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