| Project/Area Number |
02452166
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | Kyoto University (1991)
Kyushu University (1990) |
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Principal Investigator |
TOMITA Shinji Kyoto Univ., Dept. of Computer Science, Professor, 工学部, 教授 (40026323)
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| Co-Investigator(Kenkyū-buntansha) |
MURAKAMI Kazuaki Kyushu Univ., Dept. of Information Systems, Assist. Professor, 大学院総合理工学研究科, 助手 (10200263)
SHIBAYAMA Kiyoshi Kyoto Univ., Dept. of Computer Science, Associ. Professor, 工学部, 助教授 (70127091)
FUKUDA Akira Kyushu Univ., Dept. of Information Systems. Associ. Professor, 大学院総合理工学研究科, 助教授 (80165282)
吉田 紀彦 九州大学, 工学部, 助手 (00182775)
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| Project Period (FY) |
1990 – 1991
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| Project Status |
Completed (Fiscal Year 1991)
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| Budget Amount *help |
¥5,700,000 (Direct Cost: ¥5,700,000)
Fiscal Year 1991: ¥2,400,000 (Direct Cost: ¥2,400,000)
Fiscal Year 1990: ¥3,300,000 (Direct Cost: ¥3,300,000)
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| Keywords | Superscalar processor / Instruction pipeline / Optimized compiler / Code scheduling / Branch prediction / Load / store architecture / Interrupt architecture / Low-level parallelism / ス-パ-スカラ・プロセッサ |
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| Research Abstract |
The purpose of this research is to exploit parallelism at instruction level and to investigate various performance improvement techniques for superscalar architecture. Main results of the research are the following :
l. Basic control mechanism for superscalar processor
Various techniques for improving the performance are proposed and verified to be effective by software simulation. These techniques include ; (1) Four-instruction-multiplexed pipelining scheme with in-order issue and out-of-order execution strategy. This scheme not only attains high-speed execution but also reduces hardware cost drastically. (2) Powerful branch prediction mechanism in which the branch target buffer and static branch prediction methods are combined. Together with the early branch resolution, this gives a great contribution to preventing control hazards. (3) New mechanism to escape imprecise interruption, (4) Static resolution method against load/store hazards.
2. Optimizing compiler
Optimizing compiler plays an essential role in improving the performance of superscalar processor. A software pipeline scheme, a loop-unrolling scheme and a powerful combination of these schemess are investigated and verified to be effective by simulation. Maximally 5 times higher performance can be gained.
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