| Project/Area Number |
02555068
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| Research Category |
Grant-in-Aid for Developmental Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | Osaka University |
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Principal Investigator |
SHIAKAWA Isao Osaka Univ., Faculty of Engineering, Professor, 工学部, 教授 (10029100)
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| Co-Investigator(Kenkyū-buntansha) |
ISHIURA Nagisa Osaka Univ., Faculty of Engineering, Lecutrer, 工学部, 講師 (60193265)
DEGUCHI Hiroshi Osaka Univ., Computation Center, Lecutrer, 大型計算機センター, 講師 (30197826)
ARAKI Toshiro Osaka Univ., Faculty of Engineering Science, Assoc. Professor, 基礎工学部, 助教授 (70107077)
KUMAGAI Sadatoshi Osaka Univ., Computation Center, Professor, 大型計算機センター, 教授 (10093410)
MIYAHARA Hideo Osaka Univ., Faculty of Engineering Science, Professor, 基礎工学部, 教授 (90029314)
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| Project Period (FY) |
1990 – 1991
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| Project Status |
Completed (Fiscal Year 1991)
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| Budget Amount *help |
¥10,700,000 (Direct Cost: ¥10,700,000)
Fiscal Year 1991: ¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 1990: ¥7,100,000 (Direct Cost: ¥7,100,000)
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| Keywords | Computer-Aided Design / VLSI / Parallel Processing / Circuit Simulation / Logic simulation / Fault / Simulation / Routing |
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| Research Abstract |
We carried out researches on parallel processing techniques for computer-aided design (CAD) of VLSIs and developed some CAD systems. Obtained results are as follows :
1. We developed a waveform relaxation method applicable to bipolar digital circuits.
2. We developed a parallel logic simulator using distributed time management approach. We constructed a CAD engine for the logic simulation using transputers which are microprocessors suitable for paxallel processing. We also implemented logic simulators on other parallel computers and made experiments for performance evaluation.
3. As to fault simulation, we developed two methods : one uses fault collapsing for reducing the number of faults in gate level circuits, and the other is applicable to sequential circuits with bidirectional elements. We also developed a linear time fault simulation algorithm using a context addressable memory.
4. We developed a distributed system for multilayer VLSI routing using rip-up reroute method. We implemented it on a distributed processing system consisting of workstations connected by a network and evaluated the performance.
5. We constructed a integrated programming environment for occam using a window system on a generalpurpose workstation.
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