| Project/Area Number |
02555073
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| Research Category |
Grant-in-Aid for Developmental Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | Kyushu Institute of Technology |
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Principal Investigator |
SASAO Tsutomu Kyushu Institute of Technology Department of Computer Science and Technology, Associate Professor, 情報工学部, 助教授 (20112013)
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| Co-Investigator(Kenkyū-buntansha) |
KODA Norio Tokuyama College of Technology Department of Computer Science and Technology, Pr, 情報電子工学科, 教授 (10099864)
SASAO Tsutomu Kyushu Institute of Technology Department of Computer Science and Electronics, A (20112013)
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| Project Period (FY) |
1990 – 1992
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| Project Status |
Completed (Fiscal Year 1992)
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| Budget Amount *help |
¥4,400,000 (Direct Cost: ¥4,400,000)
Fiscal Year 1992: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 1991: ¥600,000 (Direct Cost: ¥600,000)
Fiscal Year 1990: ¥3,100,000 (Direct Cost: ¥3,100,000)
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| Keywords | Programmable Gate Array / Binary Decision Diagrams / Functional Decomposition / Multi-level Logic Synthesis / Reed-Muller Expansion / 論理設計 / 論理合成 / PGA / プログラマブル・ゲ-トアレイ / LSlのCAD / 多段論理回路 / PLA / 算術回路 / LSIのCAD / EXOR |
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| Research Abstract |
Field programmable gate arrays (FPGAs) are devices that can be programmed by the user to implement a logic function. Because of short turnaround time, they are becoming increasingly important for rapid prototyping. In addition, they are inexpensive to manufacture. All FPGA architectures consist of repeated arrays of identical logic blocks. A logic block is a versatile configuration of logic elements that can be programmed by the user. The interconnections for the circuit are also programmed. Among various FPGA architectures, we consider the Look up table(LUT) type FPGA where each logic block can realize an arbitrary 5 variable function. In such a FPGA., both logic bloc ks and the interconnections are programmable.
In this research, we developed a method for designing LUT type FPGAs by functional decomposition. LUT type FPGAs consists of 5-input LUTs. The outline of the method is 1) Find a decomposition of the form f=g (h(X1),X2), where X2 contains two variables, and the column multiplicities are equal to or less than 8. We have developed an efficient way to find such a decomposition by using Binary Decision Diagrams (BDDs). A function whose column multiplicity is equal to or less than eight is realized by a network for h(X1) with three outputs, followed by a 5-input LUT. The LUT has three inputs from the network for h(X1), and two inputs for X2.2) Decompose the functions recursively until the functions can be realized by 5-input LUTs. This algorithm produced solutions competitive to the previously published methods. Produced networks have regular interconnections, and easily implemented by FPGAs.
As a design method for FPGAs, we also developed a design method for AND-EXOR circuits. In many cases, AND-EXOR circuits require fewer connections and gates than AND-OR circuits to realize same function.
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