A Study on Parallel Processing for VLSI Layout
| Project/Area Number |
02650270
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | Hiroshima University |
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Principal Investigator |
YOSHIDA Noriyoshi Hiroshima Univ., Faculty of Engineering, Professor, 工学部, 教授 (60037728)
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| Co-Investigator(Kenkyū-buntansha) |
MIYAO Jun'ichi Hiroshima Univ., Faculty of Integrated Arts and Sciences, Assoc. Prof., 総合科学部, 助教授 (30200124)
WAKABAYASHI Shin'ichi Hiroshima Univ., Faculty of Engineering, Assoc. Prof., 工学部, 助教授 (50210860)
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| Project Period (FY) |
1990 – 1991
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| Project Status |
Completed (Fiscal Year 1991)
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| Budget Amount *help |
¥2,200,000 (Direct Cost: ¥2,200,000)
Fiscal Year 1991: ¥1,000,000 (Direct Cost: ¥1,000,000)
Fiscal Year 1990: ¥1,200,000 (Direct Cost: ¥1,200,000)
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| Keywords | VLSI / Layout Design / Parallel Processing / Parallel Algorithm / Placement / Routing / Graph Partitioning / Simulator / フロアプランニング / 概略配線 / 詳細配線 |
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| Research Abstract |
Results obtained in this research are summarized below.
1. Development of algorithms for building-block layout : We developed a hierarchical floorplanning method which determines floorplan and detailed routing together in a hierarchial fashion. Furthermore, we devised an optimal linear time algorithm for channel pin assignment.
2. Development of algorithms for gate-array layout : We developed an algorithm for timing-driven placement of cells in a gate-array chip. Furthermore, we devised a global routing method for large gate-array with over-the-cell routing. These methods can be easily modified to parallel algorithms, which can obtain better results in short computation time compared with existing methods.
3. Development of a parallel algorithm development system : We implemented a simulator for evaluating parallel algorithms on a workstation. Computation model of the simulator was a shared memory shared bus type multiprocessor. The simulator can produce a detailed simulation data such as hit ratio of cache. We also developed a processor scheduling algorithm for DOACROSS parallelization of sequential loops so that efficient execution of parallel algorithms becomes possible.
4. Development of parallel layout algorithms : We devised a parallel algorithm for the problem of partitioning a graph, which is one of the fundamental problems in VLSI layout design. The algorithm was evaluated from both theoretical and experimental points of view. We also developed a parallel module placement algorithm based on a parallel graph partitioning algorithm. These algorithms showed that introducing parallel processing into VLSI layout design is quite effective to obtain good design in a short design time.
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Report
(3 results)
Research Products
(18 results)
