| Project/Area Number |
02650304
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
計測・制御工学
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| Research Institution | Kobe University |
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Principal Investigator |
HANEDA Hiromasa Kobe University, Dept.of Elec.& Electr.Eng., Professor, 工学部, 教授 (10031113)
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| Co-Investigator(Kenkyū-buntansha) |
KIMURA Shinji Kobe University, Dept.of Elec.& Electr.Eng., Assistant Professor, 工学部, 助手 (20183303)
OHTA Yuzo Kobe University, Dept.of Elec.& Electr.Eng., Associate Professor, 工学部, 助教授 (80111772)
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| Project Period (FY) |
1990 – 1992
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| Project Status |
Completed (Fiscal Year 1992)
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| Budget Amount *help |
¥2,300,000 (Direct Cost: ¥2,300,000)
Fiscal Year 1992: ¥300,000 (Direct Cost: ¥300,000)
Fiscal Year 1991: ¥400,000 (Direct Cost: ¥400,000)
Fiscal Year 1990: ¥1,600,000 (Direct Cost: ¥1,600,000)
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| Keywords | Multiple DSP's / Digital Control / Minimum Throughput / Verification / Scheduling / Parallel Processing / ディジタル信号処理プロセッサ / ディジタル制御 / タイミング / スル-プット |
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| Research Abstract |
1.Modeling Multi-Processor Digital Controllers and Their Synchronization Scheme
Each processor is required to observe timing constraints to avoid command signal collision and is preferred not to have idling time intervals. Appropriate models have been investigated and selected for both feedback-type and program-controlled-type controllers with an emphasis on the verification of synchronization capabilities. It was concluded that discrete-time system representation is appropriate when viewed from digital side. We have adopted a gain matrix model for the state feedback and discrete-time transfer matrix model for program control. As a by-product, it was learned that robust stability compensation method is not mature enough for applications. Hence, we have investigated/developed a new and more useful stabilization method.
2.Minimum Throughput-Time Configuration and Synchronization Control
For single input and single output controllers, a shared memory and bus configuration was proposed. We ha
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ve investigated computational loading mechanism among each processor and proposed a new synchronization which achieves the minimum through-put time. The results were also extended to multiple-input and multiple-output cases.
3.Verifying The Proposed Scheme
Several supporting computer-software tools have been developed to verify those proposed schemes and also to be utilized in the process of design : Digital Signal Processor Command Generator, Throughput Estimator and Hybrid Simulator. Digital Signal Processor Command Generator gives program list written in the processor's command for a given digital-controller characteristics, the configuration and synchronization control protocol. Throughput Estimator evaluates throughput efficiency of a given control program. Hybrid Simulator simulates those digital control systems which include analog plant, A/D and D/A converters and digital controllers. Users can select different types of converters with different arithmetic employed and plants can be modeled as a block diagram using elementary blocks. Less
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