| Project/Area Number |
03555067
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| Research Category |
Grant-in-Aid for Developmental Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
電子通信系統工学
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| Research Institution | Tohoku University |
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Principal Investigator |
KAWAMATA Masayuki Tohoku Univ. Faculty of Eng., Associate Prof., 工学部, 助教授 (70153004)
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| Project Period (FY) |
1991 – 1992
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| Project Status |
Completed (Fiscal Year 1992)
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| Budget Amount *help |
¥10,300,000 (Direct Cost: ¥10,300,000)
Fiscal Year 1992: ¥1,900,000 (Direct Cost: ¥1,900,000)
Fiscal Year 1991: ¥8,400,000 (Direct Cost: ¥8,400,000)
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| Keywords | Multidimensional digital filters / State-space model / Systolic array / Behavioral description language / VLSI processor |
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| Research Abstract |
In this research, we design and evaluate highly parallel VLSI processors for real time 2-D state-space digital filters using hierarchical behavioral description language and synthesizer. The architecture of the 2-D state-space digital filtering system is a linear systolic array of homogeneous VLSI processors, each of which consists of eight processing elements (PEs) executing 1-D state-space digital filtering with multi-input and multi-output. HI-erarchical behavioral description language and synthesizer are adopted to design and evaluate PE's and the VLSI processors. One 16 bit fixed-point PE executing an (4,4)-th order 2-D state-space digital filtering is described on the basis of distributed arithmetic in about 1,200 steps by the description language and is composed of 15 K gates in terms of 2 input NAND gate. One VLSI processor which is a cascade connection of eight PEs is composed of 129 K gates and can be integrated into one 15 X 15 [mm^2] VLSI chip using 1 mum CMOS standard cell. The 2-D state-space digital filtering system composed of 128 VLSI processors at 25 MHz clock can execute a 1,024 X 1,024 image in 1.47 [m sec and thus can be applied to real-time conventional video signal processing.
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