| Project/Area Number |
03555069
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| Research Category |
Grant-in-Aid for Developmental Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | TOHOKU UNIVERSITY |
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Principal Investigator |
SAWADA Yasuji Research Institute of Electrical Communication, Tohoku University, Professor, 電気通信研究所, 教授 (80028133)
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| Co-Investigator(Kenkyū-buntansha) |
NAKAJIMA Koji Research Institute OF Electrical Communication, Tohoku University, Associate Pro, 電気通信研究所, 助教授 (60125622)
MUROTA Junichi Research Institute of Electrical Communication, Tohoku University, Associate Pro, 電気通信研究所, 助教授 (70182144)
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| Project Period (FY) |
1991 – 1992
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| Project Status |
Completed (Fiscal Year 1992)
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| Budget Amount *help |
¥16,600,000 (Direct Cost: ¥16,600,000)
Fiscal Year 1992: ¥5,000,000 (Direct Cost: ¥5,000,000)
Fiscal Year 1991: ¥11,600,000 (Direct Cost: ¥11,600,000)
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| Keywords | Neuro chip / Analog memory / Floating gate / Variable synapse / Integrated circuit / ニュ-ロチップ / 対称結合神経回路網 / 非対称結合神経回路網 / 分散記憶 |
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| Research Abstract |
1). This research attempts to clarify the problems with occur in implementation of a large-scale neural network. First, a neural A/D converter with CMOS circuits is designed. Asymmetrical synaptic weights were used to avoid the local minima problem for a neural A/D converter. Furthermore, a chip is fabricated using 4mum CMOS technology. Its successful action as an A/D converter is verified and some possible causes of misoperation of the present circuit are presented.
2). We have fabricated a microchip of a neural circuit with pulse representation. The neuron output is a voltage pulse train. The synapse is a constant current source whose output is proportional to the duty ratio of neuron output. Membrane potential is charged by collection of synaptic currents through a RC circuit, providing an analog operation similar to the biological neural system. We used a 4-bit SRAM as the memory of a synaptic weight. The expected I/O characterivtics of the neurons and the synapses were measured. We have also demonstrated the ability of the network operation by assigning the synaptic weights as an A/D converter and an associate memory.
3). A switched diffusion analog memory device(SDAM) for future analog neural networks is designed and fabricated. The device is essentially a modified floating-gate MOSFET. An existing floating-gate potential varies in inverse proportion to logarithm of number of input pulses, so the injection charge per pulse varies exponentially. In this research the floating-gate is divided into two parts to control the injection charge. One is the injection part with a small capacitance, and the other is MOSFET with a large capacitance. The two parts are connected with a thin film transistor. By the small capacitance of the injection part the injection charge per pulse can be limited and approximately constant. The fabricated SDAM was shown to have an expected performance.
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