| Project/Area Number |
03555071
|
|---|
| Research Category |
Grant-in-Aid for Developmental Scientific Research (B)
|
| Allocation Type | Single-year Grants |
|---|
| Research Field |
情報工学
|
|---|
| Research Institution | The University of Tokyo |
|---|
Principal Investigator |
TANAKA Hidehiko The University of Tokyo, Fuculty of Engineering, Professor, 工学部, 教授 (60011102)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
SAITO Tadashi The University of Tokyo, Fuculty of Engineering, Research Associate, 工学部, 助手 (90011139)
KOIKE Hanpei The University of Tokyo, Fuculty of Engineering, Lecturer, 工学部, 講師 (00215146)
|
|---|
| Project Period (FY) |
1991 – 1993
|
| Project Status |
Completed (Fiscal Year 1993)
|
| Budget Amount *help |
¥15,500,000 (Direct Cost: ¥15,500,000)
Fiscal Year 1993: ¥5,700,000 (Direct Cost: ¥5,700,000)
Fiscal Year 1992: ¥6,400,000 (Direct Cost: ¥6,400,000)
Fiscal Year 1991: ¥3,400,000 (Direct Cost: ¥3,400,000)
|
|---|
| Keywords | Parallel Processing Management / Load Balancing / Process Scheduling / Multi-Threading / Register Window / Fast Contxt Switching / Inference Processor / Performance Evaluation / マイクロカーネル / スケジュ-リング / マイクロカ-ネル / レジスタウインドウ / プロファイリング |
|---|
| Research Abstract |
This research project investigates the architecture design of a processing element for a highly parallel computer, and also investigates the management method of execution threads running on the processing element.
For this purpose, we have developed a processing element hardware which can be connected to Parallel Inference Engine PIE64 which we developed in the preveous project, We have also designd the parallel management kernel program which is running on the management processor of our processing element.
One problem on designing a processing element is a communication latency, which makes processor utilization low, and is substantial in a large scale parallel computer, To hade the latency of remote memory access, we have proposed "multi-context processing method", in which up to 4 threads can be running in a single processor sharing the common pipeline cycle by cycle. We have developed a inference processor LSI which adopts our multi-context processing method. We have shown the effectiveness of this method using this LSI chip.
Parallel management kernel is a control program running on the management processor. Parallel management kernel provides several parallel management functions such as load balancing and process scheduling. We adopt a high performance general purpose micro processor for the management processor.This micro processor adopts register window mechanism. Running parallel management management kernel on a management processor requires a fast context switching mechanism to switch execution of parallel management kernel quickly. For this purpose, we proposed a novel manegement method of a register window mechanism, and we have successfully shown the effectiveness of our method.
|
