| Project/Area Number |
03555074
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| Research Category |
Grant-in-Aid for Developmental Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | KYOTO UNIVERSITY |
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Principal Investigator |
YAJIMA Shuzo Kyoto University, Faculty of Engineering, Professor, 工学部, 教授 (20025901)
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| Co-Investigator(Kenkyū-buntansha) |
HIRAISHI Hiromi Kyoto University, Faculty of Engineering, Professor, 工学部, 教授 (40093299)
OGINO Hiroyuki Kyoto University, Faculty of Engineering, Staff, 工学部, 教務職員 (40144323)
TAKENAGA Yasuhiko Kyoto University, Faculty of Engineering, Instructor, 工学部, 助手 (20236491)
HAMAGUCHI Kiyoharu Kyoto University, Faculty of Engineering, Instructor, 工学部, 助手 (80238055)
TAKAGI Naofumi Kyoto University, Faculty of Engineering, Assoc. Professor, 工学部, 助教授 (10171422)
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| Project Period (FY) |
1991 – 1992
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| Project Status |
Completed (Fiscal Year 1992)
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| Budget Amount *help |
¥8,300,000 (Direct Cost: ¥8,300,000)
Fiscal Year 1992: ¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 1991: ¥4,800,000 (Direct Cost: ¥4,800,000)
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| Keywords | logic synthesis / logic design verification / sequential circuits / logic function optimization / state assignment / temporal logic / computer-aided logic design |
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| Research Abstract |
We carried out Research on development of logic synthesizer and design verifier for sequential circuits based on Boolean function manipulation as follows:
1. Logic synthesizer for sequential circuits based on Boolean function manipulation
For one-shot state assignment and single transition time assignment for asynchronous sequential circuits, we have proposed and implemented algorithms of finding minimum solutions based on Boolean function manipulation.
2. Design verifier for sequential circuits based on Boolean function manipulation
We have proposed a design verification algorithm based on Boolean function manipulation, which assumes, as a specification language, branching time regular temporal logic (BRTL), which has higher expressive power as compared with the conventional temporal logics. We have developed a design verifier based on the algorithm and succeeded in design verification of microprocessors.
3. Efficient Boolean function manipulation
We have clarified the theoretical properties of shared binary decision diagram (SBDD) to manipulate Boolean functions. We also have proposed and implemented an algorithm of finding input variable ordering such that the diagram becomes small and an algorithm to deal with SBDD of large size on secondary storage efficiently.
4. Graphic interface of logic synthesizer and design verifier
We have implemented a multi-computer multi-screen system by using the X window system on workstations and achieved high resolution and high-speed drawing.
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