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Study on Neural Network for Test Generation of Large Scale Logic Circuits

Research Project

Project/Area Number 03650312
Research Category

Grant-in-Aid for General Scientific Research (C)

Allocation TypeSingle-year Grants
Research Field 情報工学
Research InstitutionMeiji University

Principal Investigator

FUJIWARA Hideo  Meiji University, School of Science and Technology, Professor, 理工学部, 教授 (70029346)

Project Period (FY) 1991 – 1992
Project Status Completed (Fiscal Year 1992)
Budget Amount *help
¥2,100,000 (Direct Cost: ¥2,100,000)
Fiscal Year 1992: ¥1,000,000 (Direct Cost: ¥1,000,000)
Fiscal Year 1991: ¥1,100,000 (Direct Cost: ¥1,100,000)
KeywordsNeural Networks / Logic Circuits / Test Generation / VLSI / Algorithms / Fault Detection / ニュ-ラルネットワ-ク
Research Abstract

With the advent of VLSI and ULSI, the problem of testing logic circuits has become more and more difficult. So, it has become necessary to do research on the acceleration of automatic test generation. In this research project, we have proposed a new approach to accelerate test pattern generation using 3-valued neural networks. We have implemented a test generation system using a neural network simulator and did experiments using ISCAS benchmark circuits. Though it was predicted from the beginning, the experimental results show that the speed of software simulator of neural networks is too slow to accelerate the test pattern generation for large scale logic circuits. Especially, for the problem of test generation, only a vector corresponding to a state of the neural network which minimizes the energy of the network becomes a test pattern for the corresponding circuit. To escape from local minima in the Hopfield model, we adopted the Boltzman model. However, the experimental result shows that it is very hard to converge or find an optimal solution on the Boltzman model. The objective is to find out an approach to parallel processing which accelerates the test pattern generation for large scale logic circuits, so we also did the research on parallel test pattern generation using a network with more than one hundred workstations.

Report

(3 results)
  • 1992 Annual Research Report   Final Research Report Summary
  • 1991 Annual Research Report
  • Research Products

    (8 results)

All Other

All Publications (8 results)

  • [Publications] Hideo Fujiwara: "Three-Valued Neural Networks for Test Generation" Int.Journal of Computer Aided VLSI Design. 3. 273-290 (1991)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1992 Final Research Report Summary
  • [Publications] 藤野 貴之,藤原 秀雄: "論理回路のテスト生成のための3値ニューラルネットワークモデル" 情報処理学会論文誌. 33. 570-579 (1992)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1992 Final Research Report Summary
  • [Publications] Hideo Fujiwara: "Three-Valued Neural Networks for Test Generation" International Journal of Computer Aided VLSI Design. Vol.3. 273-290 (1991)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1992 Final Research Report Summary
  • [Publications] T.Fujino and H. Fujiwara: "A Model of Three-Valued Neural Networks to Generate Test Pattern for Logic Circuits" Journal of Information Processing Society of Japan. Vol.33. 570-579 (1992)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1992 Final Research Report Summary
  • [Publications] Hideo Fujiwara: "Three-Valued Neural Networks for Test Generation" Int. Journal of Computer Aided VLSI Design. 3. 273-290 (1991)

    • Related Report
      1992 Annual Research Report
  • [Publications] 藤野 貴之,藤原 秀雄: "論理回路のテスト生成のための3値ニューラルネットワークモデル" 情報処理学会論文誌. 33. 570-579 (1992)

    • Related Report
      1992 Annual Research Report
  • [Publications] 藤野 貴之,藤原 秀雄: "論理回路のテスト生成のための3値ニュ-ラルネットワ-クモデル" 電子情報通信学会フォ-ルトトレラントシステム研資. FTS91ー5. 33-40 (1991)

    • Related Report
      1991 Annual Research Report
  • [Publications] Hideo Fujiwara: "ThreeーValued Nearol Networks for Test Generation" International Journal of Computer Aided VLSI Design. Vol.3,No.3. 273-290 (1991)

    • Related Report
      1991 Annual Research Report

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Published: 1991-04-01   Modified: 2016-04-21  

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