| Budget Amount *help |
¥2,000,000 (Direct Cost: ¥2,000,000)
Fiscal Year 1993: ¥200,000 (Direct Cost: ¥200,000)
Fiscal Year 1992: ¥200,000 (Direct Cost: ¥200,000)
Fiscal Year 1991: ¥1,600,000 (Direct Cost: ¥1,600,000)
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| Research Abstract |
(1) After having studied the requirements for the interconnection network that can be used to develop a massively parallel computer systems to be constructed from several thousands of processors, we are convinced that the fat-tree is one of the most promising architectures. Although fat-tree is already famous as it is used in CM-5, the most important non-blocking feature of the fat tree is dismissed there. Therefore we have investigated the problems to resolved to realize the complete fat tree, and introduced a new scheme in decreasing the number of switches in the router. A prototype fat tree machine consisting of 4 processing element and 2 routers, which is developed on field programmable gate array device, is built to evaluate the performance. The date transfer rate of several mega bytes per seconds is obtained, and convinced us the element could be employed for real scale interconnection network.
(2) As a typical application of competing processor algorithm, the parallel solution of
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the automated wire-routing problem has been studied. Although quite satisfactory speedup is obtainable by the competing processor algorithm, the quality of the solution, that is, the wiring rate is less than the conventional sequential router. Therefore the problem is how to improved the quality of the solution by parallel computation. We have added the rip-up process to the competing processor wire routing algorithm, and obtained a significant improvement in the wiring rate. However, the rip-up procedure causes the increase in the computation time considerably, and we are led to the multipin net problem. Multipin net is a set of wires connected at the pin. If this net is replaced by the Steiner tree, which is a set of wires connected both at the pin and the wire, a significant improvement on the wiring rate is expected. We have developed the basic parallel algorithm for constructing a Steiner tree from the multipin network.
(3) The study of applying the competing processor algorithm to the hand-written Kanji character recognition is continued. In this year the knowledgebase for 30 representative Kanji character patterns was built and the recognition experiment was performed. In this experiment a character pattern taken from the ETL8B Kanji charter pattern database are first analyzed by the character structure analyzer and the extracted structural features are presented to 30 agents representing different character categories, which simultaneously find correspondence of each strokes using knowledgebase, and then attempts to match the presented stroke features with those in their individual database. If more than one agents recognize that the presented pattern belongs to their category, the conflict takes place. The agents in conflict compare the rules they have used or not used in the reasoning with each other and the agent which has used the deepest knowledge wins. In this experiment we have obtained almost 98% of recognition rate which is quite satisfactory. Less
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