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NEW LOGIC LSI'S HAVING SOFT HARDWARE CONFIGURATION

Research Project

Project/Area Number 04402029
Research Category

Grant-in-Aid for General Scientific Research (A)

Allocation TypeSingle-year Grants
Research Field 電子材料工学
Research InstitutionTOHOKU UNIVERSITY

Principal Investigator

SHIBATA Tadashi  Associate Professor, Dept.Electric Engineering Tohoku University, 工学部, 助教授 (00187402)

Co-Investigator(Kenkyū-buntansha) MORITA Mizuho  Associate Professor, Graduate School of Information Sciences Tohoku University, 大学院・情報科学研究科, 助教授 (50157905)
OHMI Tadahiro  Professor, Dept.Electric Engineering Tohoku University, 工学部, 教授 (20016463)
Project Period (FY) 1992 – 1993
Project Status Completed (Fiscal Year 1993)
Budget Amount *help
¥15,300,000 (Direct Cost: ¥15,300,000)
Fiscal Year 1993: ¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 1992: ¥11,700,000 (Direct Cost: ¥11,700,000)
KeywordsFunctional Device / Neuron MOS Transistor / Soft Hardware / Multi-Valued Logic / Data Matching / Multi-Valued Memory / Search Engine / CMOS / 論理LSI / ソフトハードウェアロジック / 加算器 / コンピュータアーキテクチャ / MOSLSI
Research Abstract

Integrated circuits are usually called hardware because their functions cannot be altered once they were built on silicon. The purpose of this research is to develop a new Soft Hardware which can arbitrarily change its function by external control signals. Based on such new circuit concept, we have established the foundations for new architecture computers that can perform very flexible information processing.
A high-functionality transistor called Neuron MOSFET(vMOS) which we invented and developed has allowed us to explore such new-concept circuits. Several test circuits were fabricated using double-polysilicon CMOS process and the concepts have been experimentally verified. It has been demonstrated that two-input and three-input soft-hardware logic circuits can change their logic functions such as OR, AND, EXOR, EXNOR, INHIBIT, MAJORITY VOTER etc. in real time according to the external control signals. A real-time data matching circuit having real-time variable window has been also d … More eveloped using only 10 transistors. Such circuit blocks serve as key elements to build intellignet data processing systems.
In addition, a hardware search engine has been developed also using vMOS circuitry. The hardware can find out the most similar data in a memory cell array without any software manipulation. In conventional circuits, the search for the most similar requires very time-consuming sequential data-to-data comparisons. In vMOS circuitry, however, search is performed in a fully parallel manner on hardware, thus achieving minimum latency. An intelligent memory technology has been developed also based on vMOS soft-hardware circuitry. We have developed a static memory that quantizes the incoming data into multivalued format, memorizes the data, and classifies them into various formats all at each memory cell level. A dynamic memory that memorizes an analog or multivalued data and performs an association with succeeding input data has been developed. When these memories are merged into the search engine, a new architecture for intelligent information processing systems is going to be established. Less

Report

(3 results)
  • 1993 Annual Research Report   Final Research Report Summary
  • 1992 Annual Research Report
  • Research Products

    (48 results)

All Other

All Publications (48 results)

  • [Publications] T.Shibata: "An intelligent transistor Neuron MOSFET:its impact on ULSI logic-circuits implementation" Proc.Third Int.Conf.Solid State and Integrated Circuit Technology,Beijing,China,Oct.,1992. 242-245 (1992)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] K.Kotani: "Neuron-MOS binary-logic circuits featuring dramatic reduction in transistor count and interconnections" IEDM Tech.Dig.,Dec.,1992. 431-434 (1992)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata: "Real-time reconfigurable logic circuits using neuron MOS transistors" ISSCC Dig.Technical papers,Feb.1993,FA 15.3. 238-239 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Yamashita: "Neuron MOS winner-take-all circuit and its application to associative memory" ISSCC Dig.Technical papers,Feb.1993,FA 15.2. 236-237 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata: "Neuron MOS binary-logic integrated circuits:Part I,Design fundamentals and soft-hardware-logic circuit implementation" IEEE Trans.Electron Devices. 40. 570-576 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata: "Neuron MOS binary-logic integrated circuits:Part II,Simplifying techniques of circuit configuration and their practical applications" IEEE Trans.Electron Devices. 40. 974-979 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata: "Neuron MOS voltage-mode circuit technology for multi-valued logic" IEICE Trans.Electronics. E76-C. 347-359 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata: "Four-terminal device-Impact of a new functional transistor on logic integrated circuits implementation" Proc.International Workshop on Process and Devices of Scaled LSI's,June,1993,Seoul. 1-6 (1993)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata: "Implementing intelligence on silicon using neuron-like functional MOS transistors" Proceedings of 7th Conf.Neural Information Processing Systems:Natural and Synthetic,1993(NIPS'93).(印刷中).

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] R.Au: "Neuron MOS multiple-valued memory technology for intelligent data processing" ISSCC Dig.Technical Papers,Feb.1994,FA 16.3. 270-271 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata: "Hardware implementation of intelligence on silicon using four-terminal devices" Proc.Int.Conf.Advanced Microelectronic Devices and Processing,Sendai,March 3-5,1994,pp.743-750.743-750 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] R.Au: "Neuron MOS multiple-valued memory technology for intelligent data processing" Proc.Int.Conf.Advanced Microelectronic Devices and Processing,Sendai,March 3-5,1994. 615-620 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] K.Kotani: "Neuron MOS binary-logic Integrated circuits" Proc.Int.Conf.Advanced Microelectronic Devices and Processing,Sendai,March 3-5. 609-614 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Ohmi: "The concept of four-terminal-device and its significance in the implementation of intelligent electronic circuits" IEICE Transactions in Electronice.(印刷中). (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata and T.Ohmi: "An intelligent transistor Neuron MOSFET : its impact on ULSI logic-circuits implementation" Proc.Third Int.Conf.Solid State and Integrated Circuit Technology, Beijing, China, Oct.242-245 (1992)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] K.Kotani, T.Shibata, and T.Ohmi: "Neuron-MOS binary-logic circuits featuring dramatic reduction in transistor count and interconnections" in IEDM Tech.Dig., Dec.431-434 (1992)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata, K.Kotani, and T.Ohmi: "Real-time reconfigurable logic circuits using neuron MOS transistors" in ISSCC Dig.Technical papers, Feb.FA 15.3. 238-239 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Yamashita, T.Shibata, and T.Ohmi: "Neuron MOS winner-take-all circuit and its application to associative memory" in ISSCC Dig. Technical papers, Feb.FA 15.2. 236-237 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata and T.Ohmi: "Neuron MOS binary-logic integrated circuits Part I, Design fundamentals and soft-hardware-logic circuit implementation" IEEE Trans.Electron Devices. Vol.40, No.3. 570-576 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata and T.Ohmi: "Neuron MOS binary-logic integrated circuits : Part II, Simplifying techniques of circuit configuration and their practical applications" IEEE Trans.Electron Devices. Vol.40, No.5. 974-979 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata and T.Ohmi: "Neuron MOS voltage-mode circuit technology for multi-valued logic" IEICE Trans.Electronics. Vol.E76-C, No.3. 347-359 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata and T.Ohmi: "Four-terminal device-Impact of a new functional transistor on logic imtegrated circuits implementation" Proc.International Workshop on Process and Devices of Scaled LSI's, June, 1993, Seoul. 1-6

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata, K.Kotani, T.Yamashita, H.Ishii, H.Kosaka, and T.Ohmi: "Implementing intelligence on silicon using neuron-like functional MOS transistors" Proceedings of 7th Conf.Neural Information Processing Systems : Natural and Synthetic, 1993 (NIPS'93). (accepted for publication).

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] R.Au, T.Yamashita, T.Shibata, and T.Ohmi: "Neuron MOS multiple-valued memory technology for intelligent data processing" ISSCC Dig.Technical Papers, Feb.1994, FA 16.3. 270-271

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata and T.Ohmi: "Hardware implementation of intelligence on silicon using four-terminal devices" the Proc.Int.Conf.Advanced Microelectronic Devices and Processing, Sendai, March 3-5. 743-750 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] R.Au, T.Yamashita, T.Shibata, and T.Ohmi: "Neuron MOS multiple-valued memory technology for intelligent data processing" Proc.Int.Conf.Advanced Microelectronic Devices and Processing, Sendai, March 3-5. 615-620 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] K.Kotani, T.Shibata, and T.Ohmi: "Neuron MOS binary-logic Integrated circuits" Proc.Int.Conf.Advanced Microelectronic Devices and Processing, Sendai, March 3-5. 609-614 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Ohmi and T.Shibata: "The concept of four-terminal-device and its significance in the implementation of intelligent electronic circuits" IEICE Transactions in Electronice.(accepted for publication).

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1993 Final Research Report Summary
  • [Publications] T.Shibata: "An intelligent transistor Neuron MOSFET: its impact on ULSI logic-circuits implementation" Proc.Third Int.Conf.Solid State and Integrated Circuit Technology,Beijing,China,Oct,1992. 242-245 (1992)

    • Related Report
      1993 Annual Research Report
  • [Publications] K.Kotani: "Neuron-MOS binary-logic circuits featuring dramatic reduction in transistor count and interconnections" IEDM Tech.Dig.,Dec.,1992. 431-434 (1992)

    • Related Report
      1993 Annual Research Report
  • [Publications] T.Shibata: "Real-time reconfigurable logic circuits using neuron MOS transistors" ISSCC Dig.Technical papers,Feb.1993,FA 15.3. 238-239 (1993)

    • Related Report
      1993 Annual Research Report
  • [Publications] T.Yamashita: "Neuron MOS winner-take-all circuit and its application to associative memory" ISSCC Dig.Technical papers,Feb.1993,FA 15.2. 236-237 (1993)

    • Related Report
      1993 Annual Research Report
  • [Publications] T.Shibata: "Neuron MOS binary-logic integrated circuits:Part I,Design fundamentals and soft-hardware-logic circuit implementation" IEEE Trans.Electron Devices. 40. 570-576 (1993)

    • Related Report
      1993 Annual Research Report
  • [Publications] T.Shibata: "Neuron MOS binary-logic integrated circuits:Part II,Simplifying techniques of circuit configuration and their practical applications" IEEE Trans.Electron Devices. 40. 974-979 (1993)

    • Related Report
      1993 Annual Research Report
  • [Publications] T.Shibata: "Neuron MOS voltage-mode circuit technology for multi-valued logic" IEICE Trans.Electronics. E76-C. 347-359 (1993)

    • Related Report
      1993 Annual Research Report
  • [Publications] T.Shibata: "Four-terminal device-Impact of a new functional transistor on logic integrated circuits implementation" Proc.International Workshop on Process and Devices of Scaled LSI's,June,1993,Seoul. 1-6 (1993)

    • Related Report
      1993 Annual Research Report
  • [Publications] T.Shibata: "Implementing intelligence on silicon using neuron-like functional MOS transistors" Proceedings of 7th Conf.Neural Information Processing Systems:Natural and Synthetic,1993(NIPS'93).印刷中.

    • Related Report
      1993 Annual Research Report
  • [Publications] R.Au: "Neuron MOS multiple-valued memory technology for intelligent data processing" ISSCC Dig.Technical Papers,Feb.1994,FA 16.3. 270-271 (1994)

    • Related Report
      1993 Annual Research Report
  • [Publications] T.Shibata: "Hardware implementation of intelligence on silicon using four-terminal devices" Proc.Int.Conf.Advanced Microelectronic Devices and Processing,Sendai,March 3-5,1994,pp.743-750. 743-750 (1994)

    • Related Report
      1993 Annual Research Report
  • [Publications] R.Au: "Neuron MOS multiple-valued memory technology for intelligent data processing" Proc.Int.Conf.Advanced Microelectronic Devices and Processing,Sendai,March 3-5,1994. 615-620 (1994)

    • Related Report
      1993 Annual Research Report
  • [Publications] K.Kotani: "Neuron MOS binary-logic Integrated circuits" Proc.Int.Conf.Advanced Microelectronic Devices and Processing,Sendai,March 3-5,1994,pp.609-614. 609-614 (1994)

    • Related Report
      1993 Annual Research Report
  • [Publications] T.Ohmi: "The concept of four-terminal-device and its significance in the implementation of intelligent electronic circuits" IEICE Transactions in Electronice.(印刷中). (1994)

    • Related Report
      1993 Annual Research Report
  • [Publications] T.Shibata: "Neuron MOS binary-logic integrated circuits: Part I-- Design fundamentals and soft-hardwaer-logic circuit implementation" IEEE Transactios on Electron Devices. 40. 570-576 (1993)

    • Related Report
      1992 Annual Research Report
  • [Publications] T.Shibata: "Neuron MOS binary-logic integrated circuits: Part II-- Simplifying techniques of circuit configuration and their practical appliations" IEEE Transations on Electron Devices. 40. (1993)

    • Related Report
      1992 Annual Research Report
  • [Publications] K.Kotane: "Neuron-MOS binary-logic circuits featuring dramatic reduction in transistor count and interconnections" IEDM Technical Digest. 431-434 (1992)

    • Related Report
      1992 Annual Research Report
  • [Publications] T.Shibata: "Real-time reconfigurable logic circuits using meuron MOS transistors" ISSCC Digest of Technical Papers. 238-239 (1993)

    • Related Report
      1992 Annual Research Report
  • [Publications] T.Yamashita: "Neuron MOS winner-take-all ciruit and its application to associatice memory" ISSCC Digest of Tchnical Papers. 236-237 (1993)

    • Related Report
      1992 Annual Research Report
  • [Publications] T.Shibata: "Neuron MOS voltage-mode circuit techmology for multi-valued logic" IEICE Tramsactins on Electronics. E76-C. (1993)

    • Related Report
      1992 Annual Research Report

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Published: 1992-04-01   Modified: 2016-04-21  

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