| Project/Area Number |
04452167
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
電子材料工学
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| Research Institution | TOHOKU UNIVERSITY |
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Principal Investigator |
MUROTA Junichi TOHOKU UNIVERSITY, RESEARCH INSTITUTE OF ELECTRICAL COMMUNICATION, ASSOCIATE PROFESSOR, 電気通信研究所, 助教授 (70182144)
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| Co-Investigator(Kenkyū-buntansha) |
MATSUURA Takashi TOHOKU UNIVERSITY, RESEARCH INSTITUTE OF ELECTRICAL COMMUNICATION, ASSOCIATE PRO, 電気通信研究所, 助教授 (60181690)
ONO Shoichi TOHOKU UNIVERSITY, RESEARCH INSTITUTE OF ELECTRICAL COMMUNICATION, PROFESSOR, 電気通信研究所, 教授 (00005232)
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| Project Period (FY) |
1992 – 1993
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| Project Status |
Completed (Fiscal Year 1993)
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| Budget Amount *help |
¥5,800,000 (Direct Cost: ¥5,800,000)
Fiscal Year 1993: ¥2,000,000 (Direct Cost: ¥2,000,000)
Fiscal Year 1992: ¥3,800,000 (Direct Cost: ¥3,800,000)
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| Keywords | Silicon / Silicon-Germanium / Heterostructure / Heterodevice / Ultrasmall Device / CVD / MOSFET |
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| Research Abstract |
The object of this research is to construct the fabrication process of a high performance ultrasmall device containing nanometer controlled Si_<1-x>Ge_x heterolayr. The research results are summarized as follows.
(1) A very low-temperature epitaxial growth process of the Si/Si_<1-x>Ge_x/Si heterostructure with atomically flat surfaces and interfaces for Ge fractions on Si(100) has been achieved under the cleanest possible reaction and interfaces for Ge fracions on Si(100) has been achieved under the cleanest possible reaction environment of SiH_4, GeH_4 and H_2 or Ar using an ultraclean hot-wall low-pressure CVD system. A relatively lower deposition temperatures were suitable for higher Ge fractions in order to prevent island growth of thelayrs during deposition. Atomically flat surfaces and interfaces for the heterostructure containing Si_<0.8>Ge_<0.2>, Si_<0.5>Ge_<0.5> and Si_<0.3>Ge_<0.7> layrs were obtained by deposition at 550, 500 and 450ﾟC, respectively.
(2) MOSFET's were fabricated at temparetures below 700ﾟC on the 10nm-thick Si/7nm-thick Si_<1-x>Ge_x/Si heterostructure using a self-alligned Si gate process. A high performance Si_<0.5>Ge_<0.5>-channel MOSFET has been achieved with a large mobility enhancement of about 70% at 300K and over 150% at 77K compared with that of a MOSFET without SiGe-channel.
(3) In-situ B doping control of Si_<1-x>Ge_x layr was achieved in the range of 3x10^<17>-2x10^<20>cm^<-3>. It was found that Hall mobility has a minimum value for Si_<0.75>Ge_<0.25> film, and the mobility of the strained Si_<0.75>Ge_<0.25> film is neary equal to that of the unstrained one.
(4) In-sity B doped selective SiGe epitaxial growth were achieved at 550ﾟC.Using this selective film, high performance self-aligned ultrashallow junction was formed with a low level reverse current density, the range of 10^<-10>A/cm^2. As a result, the overlap control between gate and source/drain and suppression of short channel effects in ultrasmall MOSFET can be improved.
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