| Project/Area Number |
04452198
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | Kyushu Univ. |
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Principal Investigator |
YASUURA Hiroto Kyushu Univ.. Interdisciplinary Graduate School of Engineering Sciences, Professor, 大学院・総合理工学研究科, 教授 (80135540)
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| Co-Investigator(Kenkyū-buntansha) |
SAWADA Sunao Kyushu Univ.. Engineering, Research Associate, 工学部, 助手 (70235464)
MURAKAMI Kazuaki Kyushu Univ.. Interdisciplinary Graduate School of Engineering Sciences, Lecture, 大学院・総合理工学研究科, 講師 (10200263)
岩井原 瑞穂 九州大学, 大学院・総合理工学研究科, 助手 (40253538)
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| Project Period (FY) |
1992 – 1993
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| Project Status |
Completed (Fiscal Year 1993)
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| Budget Amount *help |
¥7,100,000 (Direct Cost: ¥7,100,000)
Fiscal Year 1993: ¥1,700,000 (Direct Cost: ¥1,700,000)
Fiscal Year 1992: ¥5,400,000 (Direct Cost: ¥5,400,000)
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| Keywords | VLSI CAD / Placement and Routing, Hardware Description Language / Hardware / Software Codesign / Login Synthesis / Microprocessor / Soft Core-Processor / Layout Synthesis / ソフトコアプロセッサ / レイアウト設計 / 配線遅延 |
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| Research Abstract |
Traditional logic synthesis technology principally aims at generating topological information of logic circuits, realizing function given by functional description. Geometric information which appears in a final mask-pattern is decided in layout synthesis stage independently from logic synthesis. Therefore, in the case of random circuits like control-path, it is possible to get better performance than manual design. But, in the case of regular circuits like data-path, iti is hard to design good synthesis method in which geometric restriction on layout is considered in logic synthesis, and a design description language for that purpose.
(a) Study on design description language that canrepresent regularity of layout-pattern : We proposed a language which can specigy the regularity on layout-pattern and the outline of placement and routing information in functional design.
(b) Study on logic synthesis considering areas and wiring delays : We investigated a logic sythesis method considering wiring delays and areas in logic synthesis, and proposed a circuit synthesis method using the commutative law.
(c) Comparisons of methods to design the practical circuits : We examined the effect of the several synthesis methods, applying them to practical development of a microprocessor. We concretely point out problems on commercial tools and languages.
(d) Applocation of the logic synthesis method : As an application of our method, we propose hardware/software codesign using soft core-processor.
Through the above researches, we unified logic synthesis and layout synthesis, which have been done independently. In our method, designers specify information on layout in architecture design, and logic synthesis and layout synthesis are done using its information. We also show a framework of new design automation system and its application method.
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