| Budget Amount *help |
¥9,100,000 (Direct Cost: ¥9,100,000)
Fiscal Year 1994: ¥1,300,000 (Direct Cost: ¥1,300,000)
Fiscal Year 1993: ¥3,800,000 (Direct Cost: ¥3,800,000)
Fiscal Year 1992: ¥4,000,000 (Direct Cost: ¥4,000,000)
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| Research Abstract |
For next-generation super chips, not only computer-world applications but also real-world applications will be important targets. In the real-world applications, there is data flow passing through the real world, so that the real-world environment is changed to be the desired states by control actions. The typical applications are robotics. Especially, the target architectures rely incresingly on VLSI processors having a high degree of spatial parallelism. Such processors, capable of providing both high throughput and low latency, will be essential components in robot control because they have to respond quickly to the real-world events. In this research project, the following highest performance VLSI processorshave been developed for the first time in the world.
(1) Minimum-Latency Linear Array VLSI Processors
The key concept to minimize the latency is that each each processor element generates its output data emmediately after its input data become available, with 100% utilization of i
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ts arithmetic unit. The developed porcessors based on the concept are the inverse dynamics processor and the FFT processor for robot vision. These performances are much higher than those of the conventional ones.
(2) Reconfigurable Parallel VLSI Processor
In each processor element, a switch circuit is used to change the connection between the multipliers and adders, so that the multiple-input add-multiply can be performed effectively without communication overhead in the data transfer. For an example, the differential kinematics computation can be performed about 100 times faster in comparison with the convential parallel DSP aruchiteture.
(3) Bus-connected parallel VLSI processors
To reduce the latency, the number of communication steps is minimized by its optimal allocation formulated in an integer programming. Moreover, not only parallel operations in memory access and execuition of a task but also parallel data transfer is realized to make the communication cycle time small. To verify its validity, the universal processor is evaluated on the computation of dynamic control. Less
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