| Project/Area Number |
04650313
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報工学
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| Research Institution | Kyoto Institure Of Technology |
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Principal Investigator |
SHIBAYAMA Kiyoshi Kyoto Institute of Technology, Eng. & Prof., 工芸学部, 教授 (70127091)
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| Project Period (FY) |
1992 – 1993
|
| Project Status |
Completed (Fiscal Year 1993)
|
| Budget Amount *help |
¥2,000,000 (Direct Cost: ¥2,000,000)
Fiscal Year 1993: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 1992: ¥900,000 (Direct Cost: ¥900,000)
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| Keywords | Processor-core / Massively parallel computer / Processor element / Processing function / Memory function / Communication function / Computer architecture |
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| Research Abstract |
In this research, we aimed at drastic improvements in a processor-core architecture as a processor element oriented to a massively parallel computer, on the basis of the state-of-the-art IC technology.
First of all, we have extracted indispensable and essential ones from the respective functions of processing, memory and communication. Next, we have merged them into an all-in-one processor-core function, and designed a concise processor-core architecture for several massively parallel computers.
This processor-core can provide massively parallel computer architects with a homogeneous and simple processor element architecture as a new tradeoff between hardware and software.
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