| Co-Investigator(Kenkyū-buntansha) |
NUMATA Issei Graduate School of Information Science, Japan Advanced Institute of Science and, 情報科学研究科, 助手 (50272993)
ABE Touru Graduate School of Information Science, Japan Advanced Institute of Science and, 情報科学研究科, 助教授 (80222652)
武田 利浩 (武田 浩) 山形大学, 工学部, 助手 (90236472)
TANNO Kuninobu Faculty of Engineering, Yamagata University Professor, 工学部, 教授 (40007018)
KOBAYASHI Hiroaki Graduate School of Information Science, Tohoku University Associate Professor, 工学部, 助教授 (40205480)
ASO Hirotomo Faculty of Engineering, Tohoku University Professor, 工学部, 教授 (10005522)
JAIN Vijay k. Department of Electrical Engineering, University of South Florida Professor, 電子工学科(アメリカ), 教授
LOMBARDI Fan テキサスM&A大学, 計算機科学科(アメリカ), 教授
KIM Jung h. The Center for Advanced Computer Studies, University of SW Louisiana Associate P, 先端計算機科学科(アメリカ), 準教授
KNIGHT Thoma MIT人工知能研究所(アメリカ), 主席研究員
TAKETA Hiroshi Faculty of Engineering, Yamagata University Associate Researcher
SHIMODAIRA Hiroshi Graduate School of Information Science, Japan Advanced Institute of Science and
THOMAS Knight jr. Arificial Intelligence Laboratory, MIT Professor
FABRIZIO Lambardi Department of Computer Science Taxas A & M University Professor
下平 博 北陸先端科学技術大学院大学, 情報科学研究科, 助教授 (30206239)
JAIN Vjay 南フロリダ大学, 電子工学科, 教授
LOMBARDI Fab テキサスM&A大学, 計算機科学科, 教授
KIM H.Jung ルイジアナ州立大学, 先端計算機科学科, 準教授
KNIGHT F.Tho MIT 人口知能研究所, 主席研究員
中村 維男 東北大学, 工学部, 教授 (80005454)
FABRIZIO Lom テキサスM&A大学, 計算機科学科, 教授
THOMAS F.Kni 人工知能研究所, MIT計算機科学科, 準教授主席研究員
PETER Wyatt MITリンカーン研究所, 主研究員
JUNG H.Kim ルイジアナ州立大学, 先端計算機科学センター, 助教授
|
|---|
| Budget Amount *help |
¥24,000,000 (Direct Cost: ¥24,000,000)
Fiscal Year 1995: ¥6,000,000 (Direct Cost: ¥6,000,000)
Fiscal Year 1994: ¥9,000,000 (Direct Cost: ¥9,000,000)
Fiscal Year 1993: ¥9,000,000 (Direct Cost: ¥9,000,000)
|
|---|
| Research Abstract |
This research deals with a 3D-mesh array on stacked wafers and its fault tolerant architecture. The architecture of 3D-mesh arrays provides a self-reconfiguration of interconnections using a recursive shift scheme. Anuj Chandra et al. also proposed a reconfigurable algorithm for 3D 1/ track model based on a compensation path scheme that was originally proposed S.Y.Kung et al. The 3D 1/ track model was, however, discussed only from the theoretical view points of extension of the 2D 1/ track model. This paper examines its fault tolerant performance to obtain the system yield of a 3D-mesh array using a self-reconfiguration scheme.
First, we reviews recent WSI devices to construct massively parallel computers and summarize the merit of WSI parallel computers. Next. we deal with the mesh-connected multiprocessor architecture and reconfiguration stategies to enhance the array yield for WSI implementation. Reconfiguration performance of a mesh-connected parallel computer is discussed by comparing it to previous works. WSI implementation of a cube-connected cycles (CCC) is addressed and its yield performance is discussed by taking into account the chip area of the PEs, switches, and links. We also propose a new interconnection network HCQ based on a crossed cube interconnection to reduce the diameter and the average distance of the interconnection network. The excellent network property of HCQ is theoretically investigated. Finally, we discussed a 3D-mesh array on stacked wafers for massively parallel computers. A reconfiguration algorithm based on a recursive shift scheme is proposed. Applying the recursive shift scheme to a 3D-mesh array, it is shown that the reconfiguration performance becomes high and provides the possibility to construct a massively parallel computer on stacked wafers like as the 3D-mesh array.
|
