| Project/Area Number |
05452188
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | Osaka University |
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Principal Investigator |
TANIGUCHI Kenji Osaka University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (20192180)
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| Co-Investigator(Kenkyū-buntansha) |
MORIFUJI Masato Osaka University, Faculty of Engineering, Professor, 工学部, 助手 (00230144)
HAMAGUCHI Chihiro Osaka University, Faculty of Engineering, Associate Professor, 工学部, 教授 (40029004)
森 伸也 大阪大学, 工学部, 助手 (70239614)
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| Project Period (FY) |
1993 – 1994
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| Project Status |
Completed (Fiscal Year 1994)
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| Budget Amount *help |
¥7,800,000 (Direct Cost: ¥7,800,000)
Fiscal Year 1994: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 1993: ¥7,000,000 (Direct Cost: ¥7,000,000)
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| Keywords | Single Electron Tunnel Devices / Coulomb blockade / Pseudo-CMOS logic circuits / Tunnel Capacitor / 回路シミュレーション / NAND回路 |
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| Research Abstract |
(1) Using a Monte Carlo circuit simulator, we investigated various device structures with the use of single electron tunneling (SET) phenomena. The decrease of tunnel resistance is essential to ensure high current drivabiltiy of SET devices but leads to circuit malfunctions due to co-tunneling effect. We demonstrated that there exists a suitable tunneling value depending on circuit scale.
(2) We proposed a scaling rule for SET devices. Although the down-scaling of capacitors results in the increase of drain current and applied voltage, we showed that junction-temperature-rise due to Joule heat may prohibit their normal operation.
(3) We demonstrated that "multi-electron" logic instead of "single-electron" is suitable for stable SET circuit operation since electronic charge in a rather large load capacitor screens electron in a control node which is confirmed by simulations of inverter chain circuits. We found that the best load capacitor would be a "15-electron" logic from a view point of a trade-off between switching time and dissipation power.
(4) We established basic process technologies utilizing our EB direct writing to fabricate SET devices on GaAs/AlGaAs hetero-structures.
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