| Project/Area Number |
05452209
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
System engineering
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| Research Institution | TOKYO INSTITUTE OF TECHNOLOGY (1995)
Japan Advanced Institute of Science and Technology (1993-1994) |
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Principal Investigator |
KAJITANI Yoji Tokyo Inst.of Tech., Faculty of Engrg., Professor, 工学部, 教授 (00016536)
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| Co-Investigator(Kenkyū-buntansha) |
TAKAHASHI Atushi Tokyo Inst.of Tech., Faculty of Engrg., Research Associate, 工学部, 助手 (30236260)
FUJIYOSHI Kunihiro JAIST,School of Information Science, Research Associate, 情報科学, 助手 (80242569)
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| Project Period (FY) |
1993 – 1995
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| Project Status |
Completed (Fiscal Year 1995)
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| Budget Amount *help |
¥7,200,000 (Direct Cost: ¥7,200,000)
Fiscal Year 1995: ¥600,000 (Direct Cost: ¥600,000)
Fiscal Year 1994: ¥1,900,000 (Direct Cost: ¥1,900,000)
Fiscal Year 1993: ¥4,700,000 (Direct Cost: ¥4,700,000)
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| Keywords | VLSI CAD / placement / logic circuit / delay / floor plan / routing / layout / synchronous circuit / VLSI / テクノロジマッピング / フロアプラン / パス遅延 / 矩形限定 / FPGA / 組み合せアルゴリズム |
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| Research Abstract |
Two main results obtained in research for automated design system of the delay controlled logic circuits are described in the following.
1. High speed logic by controlling clock time :
Given a maximum and minimum signal delay of each line segment, a formula for an optimum clock scheduling is developed to provide exact time on which the clock should be provided to each register. A clock distribution with certain allowance to the assigned time is proposed with experiments to verify the idea being effective compared with the conventional methods which aim to reduce both skew of colck time and signal delay.
Peripheral technologies : Characterization of logic circuits whose signal delay of each path is observable, Construction of clock distributing trees such that the distance from the source to each leaf point is within certain bound, Delay performance driven clustering of a logic circuit.
2. Placement and routing :
(1) Expected congestion based layout : A concept of placement based on the expectd wire congestion is proposed with experiments in which a way to determine the evaluation function is offered. The latter idea will initiate a new general methodology in approach to hard problems.
(2) Meta-grid placement : Most difficulties in VLSI layout design come from the lack of practical packing technology. We proposed two methods named BSG and SEQ-PAIR.Both are similar in addressing the plane, but each has its advantage in applications. The performance of packing is shown by experiments in a simulated annealing to prove a surprisingly high quality packing of more than five hundred rectangles. Based on this technology, a layout algorithm for analog and printed circuits has been developed taking practical examples.
Peripheral technology : Optimum arrangement of cells in gate array disign.
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