| Project/Area Number |
05650352
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
情報通信工学
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| Research Institution | Nagoya Institute of Technology |
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Principal Investigator |
IWANAMI Yasunori Nagoya Institute of Technology, Department of Electrical and Computer Engineering, Associate Professor, 工学部, 助教授 (40144191)
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| Project Period (FY) |
1993 – 1994
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| Project Status |
Completed (Fiscal Year 1994)
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| Budget Amount *help |
¥1,700,000 (Direct Cost: ¥1,700,000)
Fiscal Year 1994: ¥300,000 (Direct Cost: ¥300,000)
Fiscal Year 1993: ¥1,400,000 (Direct Cost: ¥1,400,000)
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| Keywords | Radio LAN / Digital Communication / Modulation Scheme / GMSK / FSK / Sequence Estimation / Frequency Detection / Fading / 変復調 / ディジタルFM / ビット誤り率 |
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| Research Abstract |
First, we have proposed sequence estimation schemes of binary CPFSK and GMSK signals with Limiter-Discriminator and Integrate & Dump filter detection. We have also examined the Bit Error Rate (BER) of this scheme under Additive White Gaussian Noise (AWGN) channel, Rayleigh Fading channel and Rician fading channel, using exact computer simulation technique. We have confirmed that the proposed scheme improves the BER very much compared to the conventional scheme.
Second, we have proposed that the Digital Signal Processing Type Digital Phase Locked Loop (DSP DPLL) can also be used as a demodulator of the above proposed scheme. Furthermore, we have compensated the Inter-Symbol Interference (ISI) caused by the finite bandwidth of the DSP DPLL by using the sequence estimation. Computer simulation shows that the BER is improved effectively by using thie ISI compensation.
These proposed schemes can be applied to the practical modulation scheme for radio LANs. The results of this research have been presented at several international conferences and also submitted to the IEEE journal.
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