| Project/Area Number |
05680274
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機科学
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| Research Institution | HIROSHIMA UNIVERSITY |
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Principal Investigator |
WAKABAYASHI Shinichi Hiroshima Univ., Fac.of Eng., Assoc.Prof., 工学部, 助教授 (50210860)
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| Co-Investigator(Kenkyū-buntansha) |
KOIDE Tetsushi Hiroshima Univ., Fac.of Eng., Research Assoc., 工学部, 助手 (30243596)
YOSHIDA Noriyoshi Hiroshima Univ., Fac.of Eng., Professor, 工学部, 教授 (60037728)
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| Project Period (FY) |
1993 – 1994
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| Project Status |
Completed (Fiscal Year 1994)
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| Budget Amount *help |
¥1,800,000 (Direct Cost: ¥1,800,000)
Fiscal Year 1994: ¥400,000 (Direct Cost: ¥400,000)
Fiscal Year 1993: ¥1,400,000 (Direct Cost: ¥1,400,000)
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| Keywords | Meta-heuristics / VLSI / Layout design / Floorplan Design / Cell placement / Global routing / Channel routing / Genetic algorithm / 配置設計 / 配線設計 / ヒューリスティックアルゴリズム / 組合せ問題 / VLSIレイアウト設計 / シミュレーティドアニーリング / スタンダードセル |
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| Research Abstract |
In this research, we have studied the VLSI layout design methods based on meta-heuristics. For all algorithms developed in this research, we have performed simulations experiments to show their effectiveness. Summaries of the research results are as follows.
1.Hypergraph partitioning algorithms : We have developed algorithms for the hypergraph partitioning problem, which is one of the fundamental problems in VLSI layout design. In the proposed algorithms, clustering of nodes is performed to get a good solution.
2.A floorplanning method based on topological constraint manipulation : For the floorplan design of VLSI chips, we have developed a floorplanning algorithm, in which topological constraints of block placement arre dynamically changed.
3.Cell placement algorithms : We have developed two cell placement algorithms, one of which is based on genetic algorithms, and the other is a timing-driven cell placement algorithm.
4.Global routing methods : We have developed two global routing methods for standard cell layouts, whose objective is to minimize both the channel density and the total wire length.
5.Over-the-cell channel routing methods : We have proposed new cell models for standard cell layout design with over-the-cell three-layr channel routing, and developed channel routing algorithms.
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