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A Research on the Representation and Manipulation of Logical Expressions using Ternary Decision Diagrams

Research Project

Project/Area Number 05680279
Research Category

Grant-in-Aid for General Scientific Research (C)

Allocation TypeSingle-year Grants
Research Field 計算機科学
Research InstitutionKyushu Institute of Technology

Principal Investigator

SASAO Tsutomu  Kyushu Institute of Technology Department of Computer Science and Technology, Professor, 情報工学部, 教授 (20112013)

Co-Investigator(Kenkyū-buntansha) KODA Norio  Tokuyama College of Technology Deoartment of Comouter Science and Technology, Pr, 情報電子工学科, 教授 (10099864)
Project Period (FY) 1993 – 1994
Project Status Completed (Fiscal Year 1994)
Budget Amount *help
¥2,000,000 (Direct Cost: ¥2,000,000)
Fiscal Year 1994: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 1993: ¥1,500,000 (Direct Cost: ¥1,500,000)
KeywordsTernary Decision Diagrams / Binary Decision Diagrams / EXOR Logic / Field Programmable Gate Array / BDD / TDD
Research Abstract

We considered methods to represent logic functions by using Ternary Decision Diagrams (TDDs).
(1) Termary Decision Diagrams and Their Applications.
AND Ternary Decision Diagrams (ATDD) : Suppose that a logic function f is expanded as f=xf0Vxfl. In a binary decision diagram (BDD), the node for f has two sub trees representing f0 and f1. In ATDD,the node for f has three sub tree representing f0, f1, and f2, where f2=f0 ・ f1. An ATDD implicitly represents a set of prime implicamts (PIs). We developed a program to generate a set of PIs using ATDDs. This method is mucg more efficient than ordinary methods, and we successfully generated sets of millions of PIs. We also obtained the upper bound on the size of memory required to represent ATDDs.
EXOR Termary Decision Diagrams (ETDD) : In ETDD,the node for f has three sub tree representing f0, f1, and f2, where f2=f0 <symmetry> f1. ETDDs are useful to simplify various AND-EXOR expressions.
(2) Optimization of Various AND-EXOR Expressions.
Various cl … More asses exist in AND-EXOR expressions : FPRM (Fixed Polarity Reed-Muller expression), KRO (Kronecker expression), PSDKRO (pseudo-Kronecker expression), GRM (Generalized Reed-Muller expression), and ESOP (EXOR sum-of-products expression).ETDDs are useful to optimize these expressions.
ESOPs require the fewest products among these expressions, but the optimization is, in general, difficult. We developed EXMIN2, a heuristic minimization program for ESOPs. EXMIN2 uses ten rules. We also analized the set of rules to obtain optimum ESOPs. For the ESOPs with small number of inputs, we can obtain an exact minimum ESOPs by using exhaustive methods. We obtained all the minimum ESOPs up to 5 variables. We also developed a simplification program using the results of exact minimum ESOPs. We also developed an exact minimization method for ESOPs, using BDDs. This program is useful for the fumctions with up to n=6 variables.
GRM is a sub-class of ESOPs. We developed an easily testable realization for GRMs. We developed 1)an exact minimization method for GRMs by using BDDs, and 2)a heuristic simplification method using iterative improvement method.
FPRM is a sub-class of GRMs. Optimization methods for FPRMs have beenstudied for many years. We developed a method to obtain exact minimum FPRMs by using multi-terminal EXOP ternary decision diagrams. By using this method, we successfully minimized the FPRMs with more than 90 inputs and many outputs. The conventional methods can minimize FPRMs with up to 16 inputs.
PSDKRO is a sub-class of ESOPs. We developed a minimization program for PSDKROs by using ETDDs. This method is much faster than EXMIN2, and can beused as pre-minimization algorithm for ESOPs. We are developing a minimization method for ESOP using ETDDs. Less

Report

(3 results)
  • 1994 Annual Research Report   Final Research Report Summary
  • 1993 Annual Research Report
  • Research Products

    (42 results)

All Other

All Publications (42 results)

  • [Publications] 笹尾勤: "FPGAの論理設計法" 情報処理. 35. 530-534 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] Jon T. Butler and Tsutomu Sasao: "Multiple-valued Combinational Circuits with Feedback" ISMVL-94. 342-347 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] Tsutomu Sasao and Jon T.Butler: "A Desing Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion" ISMVL-94. 97-106 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] R. S. Stankovic, M. Stankovic, C. Moraga and T. Sasao: "The Calculation of Reed-Muller Coefficients of Multiple-Valued Functions through Multi-Place Decision Diagrams" ISMVL-94. 82-88 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T. Sasao: "Easily Testable Realization for Generalized Reed-Muller Expressions" IEEE The 3rd Asian Test Symposium. 157-162 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T. Sasao and D. Debnath: "An exact minimization algorithm for generalized Reed-Muller expressions IEEE Asia-Pacific Conference on Circuits and Systems" APCCAS'94. 460-465 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] 笹尾勤: "論理設計:スイッチング回路理論" 近代科学社, 290 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T.Sasao: ""Optimization of pseudo-Kronecker expressions using multipleplace decision diagrams"" IEICE Transactions on Information and Systems. 562-570 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T.Sasao, EXMIN2: "A simplification algorithm for exclusive-OR-Sum-of-products expressions for multiple-valued input two-valued output functions" IEEE Transactions on Computer-Aided Desigh of Integrated Circuits and Systems. vol.12, No.5. 621-632 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] D.Brand and T.Sasao: ""Minimization of AND-EXOR expressions using rewriting rules"" IEEE Tramsactions on Computers. Vol.42, No.5. 568-576 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T.Sasao: ""Ternary decision diagrams and their applications"" International Workshop on Logic Synthesis, Tahoe City, California. 23-26 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] N.Koda and T.Sasao: ""LP-Characteristic vectors of logic functions and their applications"(in Japanese)" Trans. IEICE Japan, Part D-I. Vol.J76-D-1, No.6. 260-268 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T.Sasao: ""An exact minimization of AND-EXOR expressions using BDDs"" IFIP 10.5 Workshop on Application of the Reed-Muller expansion in Circutit Design. (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] N.Koda and T.Sasao: ""LP equivalence class of logic functions"" IFIP 10.5 Wordshop on Application of the Reed-Muller expansion in Circuit Design. (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T.Sasao: ""An exact minimization of AND-EXOR expressions using reduced covering functions" "Proc.of the Synthesis and Simulation Meeting and International Interchange. 374-383 (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T.Sasao and M.Matsuura: ""A minimization metod for AND-EXOR expressions using BDDs"(in Japanese)" Technical Report.IEICE Japan. FTS93-34. (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] N.Koda and T.Sasao: ""EXBOUND : A minimization algorithm for multipleoutput AND-EXOR expressions"" Technical Report, IEICE Japan. FTS93-35. (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T.Sasao and K.Okamura: ""A design method for FPGA useng functional decomposition"(in Japanese)" Technical Report, IEICE Japan. FTS93-36. (1993)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] J.T.Butler and T.Sasao: ""Multiple-valued combinational circuits with feedback"" IEEE ISMVL-94. 342-347 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T.Sasao and J.T.Butler: ""A design method for look-up table type FPGA by pseudo-Kronecker expansion"" IEEE ISMVL-94. 97-106 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] R.S.Stankovic, M.Stankovic, C.Moraga, and T.Sasao: ""The calculation of Reed-Muller coefficients of multiple-valued funcions through multi-place decision diagrams"" IEEE ISMVL-94. 82-88 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T.Sasao: ""Logic design of FPGAs"(in Japanese)" Jo-Ho-Shori. Vol.35, No.6. 530-534 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T.Sasao: ""Easily testable realization for generalized Reed-Muller expressions"" IEEE The 3rd Asian Test Symposium, November 15-17,1994, Nara Japan. 157-162

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T.Sasao and D.Debnath: ""An exact minimization algorithm for generalized Reed-Muller expressions"" IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'94) December 5-8,1994, Taipei, Taiwan. 460-465

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T.Sasao and F.Izuhara: ""Optimization of FPRMs by using multiple-terminal termary decision diagrams"(in Japanese)" Technical papers of IPSJ. DA-74-2. (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T.Sasao and H.Hamachi and S.Wada: ""Generation of AND-EXOR multi-level networks from pseudo-Kronecker decision diagrams"(in Japanese)" Technical papers of IPSJ. DA-74-3. (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] D.Debnath and T.Sasao: ""GRMIN : A heuristic simplification alhorithm for generalized Reed-Muller expressions"" Technical papers of IPSJ. DA-74-4. (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] N.Koda and T.Sasao: ""A simplification program for symmetric functions, (in Japanese)" Technical papers of IPSJ. DA-74-5. (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] T.Sasao: Logic Design : Switching Circuit Theory, (in Japanese). Kindai Kagaku Publishing Company, (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] 笹尾 勤: "FPGAの論理設計法" 情報処理. 35. 530-534 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] Jon T. Butler and Tsutomu Sasao: "Multiple-valued Combinational Circuits with Feedback" ISMVL-94. 342-347 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] Tsutomu Sasao and Jon T. Butler: "A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion" ISMVL-94. 97-106 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] R. S. Stankovic, M. Stankovic, C. Moraga, and T. Sasao: "The Calculation of Reed-Muller Coefficients of Multiple-Valued Functions through Multi-Place Decision Diagrams" ISMVL-94. 82-88 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] T. Sasao: "Easily Testable Realization for Generalized Reed-Muller Expressions" IEEE The 3rd Asian Test Symposium. 157-162 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] T. Sasao and D. Debnath: "An exact minimization algorithm for generalized Reed-Muller expressions IEEE Asia-Pacific Conference on Circuits and Systems" APCCAS'94. 460-465 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] 笹尾 勤: "論理設計:スイッチング回路理論" 近代科学社, 290 (1995)

    • Related Report
      1994 Annual Research Report
  • [Publications] T.Sasao: "Optimization of pseudo-Kronecker expressions using multiple-place decision diagrams" IEICE Transactions on Information and Systems. 562-570 (1993)

    • Related Report
      1993 Annual Research Report
  • [Publications] T.Sasao: "EXMIN2:A simplification algorithm for exclusive-OR-Sum-of-products expressions for multiple-valued input two-valued output functions" IEEE Transactions on Computer-Aided Design of Integrated Circuits andSystems. vol.12 No.5. 621-632 (1993)

    • Related Report
      1993 Annual Research Report
  • [Publications] Daniel Brand and T.Sasao: "Minimization of AND-EXOR expressions using rewriting rules" IEEE Transactions on Computers. Vol.42 No.5. 568-576 (1993)

    • Related Report
      1993 Annual Research Report
  • [Publications] 神田徳夫,笹尾勤: "論理関数のLP特徴ベクトルとその応用" 電子情報通信学会論文誌D-1. J76-D-1 No.6. 260-268 (1993)

    • Related Report
      1993 Annual Research Report
  • [Publications] T.Sasao: "Ternary decision diagrams and their applications" International Workshop on LogicSynthesis. 23-26 (1993)

    • Related Report
      1993 Annual Research Report
  • [Publications] N.Koda and T.Sasao: "LP equivalence class of functions21GC06:IFIP 10.5 Workshop on Application of the Reed-Muller expansion in Circuit Design" (1993)

    • Related Report
      1993 Annual Research Report

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Published: 1993-04-01   Modified: 2016-04-21  

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