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Low Power Logic Circuits by Energy Packet Transfer Method

Research Project

Project/Area Number 05805033
Research Category

Grant-in-Aid for General Scientific Research (C)

Allocation TypeSingle-year Grants
Research Field 電子デバイス・機器工学
Research InstitutionUniversity of Tokyo

Principal Investigator

ASADA Kunihiro  University of Tokyo, Fuc. of Engineering, Associate Prof., 工学部, 助教授 (70142239)

Project Period (FY) 1993 – 1994
Project Status Completed (Fiscal Year 1994)
Budget Amount *help
¥2,000,000 (Direct Cost: ¥2,000,000)
Fiscal Year 1994: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 1993: ¥1,200,000 (Direct Cost: ¥1,200,000)
Keywordsenergy packet transfer / charge recycle / sense amplifier logic / lowpower circuit / エネルギーパケット / パストランジスタロジッック / センスアンプロジック / ウェーブパイプライン / 低振幅ロジック / LCRロジック / エネルギーリサイクル / 低消費電力 / エネルギー下限
Research Abstract

In the present project we first studied on the lower bound of the energy consumed at the gate electrode of MOSFETs. Here we introduced a new term in the conventional gradual-channel approximation, which takes into account the lateral electric field in order to improve the model. Based on the new model we inplemented a numerical analysis program and analyzed SOI devices as samles under ultra-fast switching operation. Results showed that about 30% of the total energy supplied to the gate electrode is really consumed by the devices and the rest can be theoretically recovered by the charge recycle concept.
Next we investigated two kinds of energy-packed transfer circuits ; CR type and LCR type. The former is composed of Capacitors and Resisters ; where signals attenuated along logic paths are restored by sense amplifiers. The latter uses additional inductors, L,so as to make the efficiency of energy transfer higher. We numerically found the optimal conditions of the circuit parameters for the both circuits.
In conclusion, we proposed and evaluated new circuitry for energy transfer method and showed its possibility and limits.

Report

(3 results)
  • 1994 Annual Research Report   Final Research Report Summary
  • 1993 Annual Research Report
  • Research Products

    (3 results)

All Other

All Publications (3 results)

  • [Publications] K. Asada M. Lee: "Ultimate Lower Bound of Power for MOS Intergrated Circuits and Their Applications" IEICE TRANS. ELECTRON.E77-C. 61-66 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] Kunihiro Asada and Mike Lee.: "Ultimate Lower Bound of Power for MOS Integrated Circuits and Their Applications" IEICE Trans. Electron.Vol.E77-C,No.7, July. 61-66 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1994 Final Research Report Summary
  • [Publications] K.Asada & M.Lee: "Ultimate Lower Bound of Power for MOS Integrated Circuits and Their Applications" IEICE TRANSACTIONS on Electronics. VOL.E77-C,NO.7. 1131-1137 (1994)

    • Related Report
      1994 Annual Research Report

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Published: 1993-04-01   Modified: 2016-04-21  

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