| Project/Area Number |
05808029
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機科学
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| Research Institution | Graduate School of Information Science Japan Adavanced Institute of Science and Technology |
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Principal Investigator |
HORIGUCHI Susumu Graduate School of Information Science Japan Adavanced Institute of Science and Technology Professor, 情報科学研究科, 教授 (60143012)
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| Co-Investigator(Kenkyū-buntansha) |
SHIMODAIRA Hiroshi Graduate School of Information Science Japan Adavanced Institute of Science and, 情報科学研究科, 助教授 (30206239)
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| Project Period (FY) |
1993 – 1994
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| Project Status |
Completed (Fiscal Year 1994)
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| Budget Amount *help |
¥1,900,000 (Direct Cost: ¥1,900,000)
Fiscal Year 1994: ¥300,000 (Direct Cost: ¥300,000)
Fiscal Year 1993: ¥1,600,000 (Direct Cost: ¥1,600,000)
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| Keywords | WSI System / Self-Reconfiguration / Self-Reconfigurable Algorithm / Massively Parallel System / Distributed System / フォールトトレランス |
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| Research Abstract |
Scientists and designers have been chalenging to get much more circuits and more functions on a chip. Wafer Scale Integration (WSI) is one of promising techonologies for developing massivelly parallel systems. There are a lot of problems remained to be solved in WSI.
The aim of this research is to study a self-reconfigurable architecture which can achieve reconfigurations of massively parallel computer on Wafer Scale Computer without global information. We proposed a self-reconfigurable algorithm based on bypass and schift technieque for mesh-interconnection multiprocessor system. The algorithm does not required for the global information of fault PEs in the system which are suitable for WSI implementation.
The proposed algorithm achieves both higher reliability and higher production yield than the graph algorithm which is requiered the global information of system. The reconfigurable algorithm for link faults and switch faults is still remained problems.
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