| Project/Area Number |
06302074
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| Research Category |
Grant-in-Aid for Co-operative Research (A)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機科学
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
NANYA Takashi Tokyo Institute of Technology, Graduate School of information Science and Engineering, Professor, 大学院・情報理工学研究科, 教授 (80143684)
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| Co-Investigator(Kenkyū-buntansha) |
YASUURA Hiroto Kyushu University, Graudate School of Science & Eng., Professor, 大学院・総合理工学研究科, 教授 (80135540)
HIROSE Masataka Hiroshima University, Faculty of Eng., Professor, 工学部, 教授 (10034406)
AMANO Hideharu Keio university, Faculty of Science & Eng., Asso.Professor, 理工学部, 助教授 (60175932)
UEDA Kazuhiro Shibaura Institute of Technology, Faculty of System Eng., Professor, システム工学部, 教授 (60203436)
HOH Kohichiro University of Tokyo, Faculty of Engineering, Professor, 工学部, 教授 (60211538)
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| Project Period (FY) |
1994 – 1995
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| Project Status |
Completed (Fiscal Year 1995)
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| Budget Amount *help |
¥16,300,000 (Direct Cost: ¥16,300,000)
Fiscal Year 1995: ¥9,500,000 (Direct Cost: ¥9,500,000)
Fiscal Year 1994: ¥6,800,000 (Direct Cost: ¥6,800,000)
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| Keywords | VLSI chip implementation service / Multi-project chip / Gate arrays / Full custom LSI / VLSI Design Education |
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| Research Abstract |
With the aim of establishing a VLSI chip implementation service which supports an advanced environment of VLSI system disign education and research in Japanese universities, we conducted a pilot project to simulate multi-project-chip design and fabrication service system in order to identify any technical and economical problems encountered by the users of this system and chip foundries. In the pilot project, NTT Electronics Technology, Inc.has undertaken to play the role of the chip foundry and the multiproject chip broker.
In 1994, eight universities submitted LSI design data in Verilog netlist description to NEL to implement them with a 0.5 micron CMOS gate array technology.
In 1995,14 research groups from 11 universities submitted full custom designs in the stream data format to implement them as a single multi-project chip with a 0.8 microm analog CMOS technology. Another fabrication experiment with the gate array implementation was also done under the same condition as the 1994 experiment.
Many problems which must be solved were indentified during the design and fabrication process for both the gate array implementation and the full custom LSI implementation. The issues which have been recognized to require further discussions towards the realization of an advanced environment for VLSI design education include ; cooperation with CAD vendors, maintenance of CAD tools, cooperation with foundries, technology update, design library, network environment, education program, staff training, publicity, and others.
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