| Project/Area Number |
06452235
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
|
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| Research Institution | Waseda University |
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Principal Investigator |
TARUI Yasuo Waseda Univ., Graduate School of Sci.& Eng., Professor, 理工学研究科, 教授 (10143629)
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| Co-Investigator(Kenkyū-buntansha) |
KUROIWA Koichi Tokyo Univ.of Agri.& Tech., Dept.of Eng., Professor, 工学部, 教授 (20170102)
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| Project Period (FY) |
1994 – 1996
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| Project Status |
Completed (Fiscal Year 1996)
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| Budget Amount *help |
¥7,200,000 (Direct Cost: ¥7,200,000)
Fiscal Year 1996: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 1995: ¥2,500,000 (Direct Cost: ¥2,500,000)
Fiscal Year 1994: ¥3,600,000 (Direct Cost: ¥3,600,000)
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| Keywords | ferroelectric material / memory / PbTiO_3 / Ceria / YSZ / heteroepitaxy / acaling rule / SBT / C-V特性 / デジタルCVD |
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| Research Abstract |
The ferroelectric memories are nonvolatile and are thought to be high-speed devices, thus making them suitable for universal applications. Among many candidate, ferrolectric memories using the fieldeffect of a semiconductor by the remanent polarization of a ferro-electric material are in accordance with the scaling rule, and potentially could have low power high speed nonvolatile memories.
However, it is necessary to optimize the interface between the semiconductor and the ferroelectic material. Experiments on prospective devices using CeO_2 or Ce_xZr_<1-x>O_2 as the buffer insulator layrs of the MFIS transistors were performd with good results.
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