| Project/Area Number |
06452247
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| Research Category |
Grant-in-Aid for General Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
System engineering
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| Research Institution | Osaka University |
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Principal Investigator |
SHIRAKAWA Isao Osaka University, Department of Information Systems Engineering Professor, 工学部, 教授 (10029100)
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| Co-Investigator(Kenkyū-buntansha) |
ONOYE Takao Osaka University, Department of Information Systems Engineering Research Assista, 工学部, 助手 (60252590)
SHIGEHIRO Yuji Osaka University, Education Center for Information Processing Research Assistant, 情報処理教育センター, 助手 (40243175)
ISHIURA Nagisa Osaka University, Department of Information Systems Engineering Associate Profes, 工学部, 助教授 (60193265)
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| Project Period (FY) |
1994 – 1995
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| Project Status |
Completed (Fiscal Year 1995)
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| Budget Amount *help |
¥6,100,000 (Direct Cost: ¥6,100,000)
Fiscal Year 1995: ¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 1994: ¥2,600,000 (Direct Cost: ¥2,600,000)
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| Keywords | high-level synthesis / VLSI implementation / multithreaded architecture / processor / MPEG2 / 画像生成 / 高速合成 / マルチスレッド / ASIC / CAD |
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| Research Abstract |
In this project, we attempted VLSI implementation of processors based on a new architecture called multithreaded processing, which aims at boosting the processing speed of digital image generation.
A multithreaded processor has multiple instruction decoders and register files to execute multiple instruction streams (threads), with functional units shared by the threads for high operating ratio. Although the architecture is both cost-effective and high in performance, there had been no reported implementation because the control of multiple threads on shared functional units was highly complicated and thus made the design difficult.
We made use of high-level synthesis system to meet this problem ; we designed the control unit of the processor in behavioral specification language and then compile them into hardware by the synthesis system. This approach significantly the reduced the design complexity and made the VLSI implementation of a multithreaded processor possible.
We also made investigation to support this approach ; we developed a new algorithm for high-level synthesis, highly memory efficient data structure of logic function for logic synthesis, and an systematic approach for module clustering in VLSI layout.
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