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VLSI Implementation of New Architectures Using High-Level Synthesis System-Design of Multithreaded Processor

Research Project

Project/Area Number 06452247
Research Category

Grant-in-Aid for General Scientific Research (B)

Allocation TypeSingle-year Grants
Research Field System engineering
Research InstitutionOsaka University

Principal Investigator

SHIRAKAWA Isao  Osaka University, Department of Information Systems Engineering Professor, 工学部, 教授 (10029100)

Co-Investigator(Kenkyū-buntansha) ONOYE Takao  Osaka University, Department of Information Systems Engineering Research Assista, 工学部, 助手 (60252590)
SHIGEHIRO Yuji  Osaka University, Education Center for Information Processing Research Assistant, 情報処理教育センター, 助手 (40243175)
ISHIURA Nagisa  Osaka University, Department of Information Systems Engineering Associate Profes, 工学部, 助教授 (60193265)
Project Period (FY) 1994 – 1995
Project Status Completed (Fiscal Year 1995)
Budget Amount *help
¥6,100,000 (Direct Cost: ¥6,100,000)
Fiscal Year 1995: ¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 1994: ¥2,600,000 (Direct Cost: ¥2,600,000)
Keywordshigh-level synthesis / VLSI implementation / multithreaded architecture / processor / MPEG2 / 画像生成 / 高速合成 / マルチスレッド / ASIC / CAD
Research Abstract

In this project, we attempted VLSI implementation of processors based on a new architecture called multithreaded processing, which aims at boosting the processing speed of digital image generation.
A multithreaded processor has multiple instruction decoders and register files to execute multiple instruction streams (threads), with functional units shared by the threads for high operating ratio. Although the architecture is both cost-effective and high in performance, there had been no reported implementation because the control of multiple threads on shared functional units was highly complicated and thus made the design difficult.
We made use of high-level synthesis system to meet this problem ; we designed the control unit of the processor in behavioral specification language and then compile them into hardware by the synthesis system. This approach significantly the reduced the design complexity and made the VLSI implementation of a multithreaded processor possible.
We also made investigation to support this approach ; we developed a new algorithm for high-level synthesis, highly memory efficient data structure of logic function for logic synthesis, and an systematic approach for module clustering in VLSI layout.

Report

(3 results)
  • 1995 Annual Research Report   Final Research Report Summary
  • 1994 Annual Research Report
  • Research Products

    (26 results)

All Other

All Publications (26 results)

  • [Publications] T. Sagishima, et. al.: "Multithreaded processor for image generation" Proc. IEEE International Symposium on Circuits and Systems. 4. 231-234 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] A. Yamada, et. al.: "Datapath scheduling for behavioral description with conditional branches" IEICE Trans. Fundamentals. E77-A-12. 1999-2009 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] M.Toyonaga, et. al.: "A new approach of fractal-analysis based module clustering for VLSI placement" IEICE Trans. Fundamentals. E77-A-12. 2045-2052 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] T. Onoye, et. al.: "High-level synthesis of a multithreaded processor for image generation" IEICE Trans. Fundamentals. E78-A-3. 322-330 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] T. Masaki, et. al.: "VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding" IEEE Trans. Circuits and Systems for video Technology. 5-5. 387-395 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] T. Onoye, et. al.: "Single chip implementation of MPEG2 decoder for HDTV level pictures" IEICE Trans. Fundamentals. E79-A-3. 330-338 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] T.Onoye, T.Masaki, H.Hirata, K.Kimura, S.Asahara, T.Sagishima, I.Shirakawa, S.Tsukiyama, and S.Shinoda: "High-level synthesis of multithreaded processor based image generator" Proc.IEEE International Symposium on Industrial Electronics. 47-52 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] K.Kimura, H.Hirata, T.Kiyohara, S.Asahara, T.Sagishima, T.Onoye, and I.Shirakawa: "Evaluation method of microarchitecture for multithreaded processor" Proc.IEEE International Symposium on Industrial Electronics. 53-58 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] T.Sagishima, K.Kimura, H.Hirata, T.Kiyohara, S.Asahara, T.Onoye, and I.Shirakawa: "Multi-threaded processor for image generation" Proc.IEEE International Symposium on Circuit and Systems. Vol.4. 231-234 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] A.Yamada, T.Yamazaki, N.Ishiura, I.Shirakawa, and T.Kambe: "Datapath scheduling for behavioral description with conditional branches" IEICE Trans.Fundamentals. Vol.E77-A,No.12. 1999-2009 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] M.Toyonaga and I.Shirakawa: "A new approach of fractal-analysis based module clustering for VLSI placement" IEICE Trans.Fundamentals. Vol.E77-A,No.12. 2045-2052 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] T.Onoye, T.Masaki, I.Shirakawa, H.Hirata, K.Kimura, S.Asahara, and T.Sagishima: "High-level synthesis of a multithreaded processor for image generation" IEICE Trans.Fundamentals. Vol.E78-A,No.3. 322-330 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] S.Nakamura, A.Yamada, and I.Shirakawa: "A heuristic scheduling algorithm for complex conditional structure" Proc.Synthesis and System Integration of Mixed Technologies. 73-78 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] T.Masaki, Y.Morimoto, T.Onoye, and I.Shirakawa: "VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding" IEEE Trans.Circuits and Systems for Video Technology. Vol.5, No.5. 387-395 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] T.Onoye, T.Masaki, Y.Morimoto, Y.Sato, I.Shirakawa, and K.Matsumura: "Single chip implementation of MPEG2 decorder for HDTV level pictures" IEICE Trans, Fundamentals. Vol.E-79A,No.3. 330-338 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] T.MASAKI et.al.: "Specific functional macrocells for MPEG2 single-chip HDTV clecoder" Proceedings of 1995 Joint Technical Conference on Circuits/Systems,Computers and Communications. 1. 499-502 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] K.OKADA et.al.: "A design of high-performance multiplier for digital video transmission" Proceedings of Asia and South Pacific Design Automation conf.1. 429-434 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] T.MASAKI et.al.: "VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding" IEEE Trans.Circuits and Systems for Video Technology. 5-5. 387-395 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] T.ONOYE et.al.: "HDTV level MPEG2 video decorder VLSI" Proceedings of International Conference on Microelectronics and VLSI. 1. 468-471 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] K.KIMURA et.al.: "Microarchitecture of Multithread Processor for Computer Graphics" Proceedings of International Conference on Neural Networks and Signal Processing. 2. 1586-1589 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] T.Onoye,T.Masaki,H.Hirata,K.Kimura,S.Asahara,T.Sagishima,I.Shirakawa,and S.Shinoda: "“High-level synthesis of multithreaded processor based image generator"" Proc.IEEE International Symposium on Industrial Electronics. 47-52 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] K.Kimura,H.Hirata,T.Kiyohara,S.Asahara,T.Sagishima,T.Onoye,and I.Shirakawa: "“Evaluation method of microarchitecture for multithreaded processor"" Proc.IEEE International Symposium on Industrial Electronics. 53-58 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] T.Sagishima,K.Kimura,H.Hirata,T.Kiyohara,S.Asahara,T.Onoye,and I.Shirakawa: "“Multithreaded processor for image generation"" Proc.IEEE International Symposium on Circuits and Systems. 4. 231-234 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] T.Onoye,T.Masaki,H.Hirata,K.Kimura,S.Asahara,T.Sagishima,S.Tsukiyama,and S.Shinoda: "“High-level synthesis of multithreaded processor for image generation :design and simulation"" Proc.European Simulation Multiconference. 948-953 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] T.Onoye,T.Masaki,S.Asahara,T.Sagishima,I.Shirakawa,S.Tsukiyama,and S.Shinoda: "“Desigu of multithreaded processor dedicated to image generation:High-level synthesis"" Proc.Joint Technical Conference on Circuits and Systems,Computers,Communication. 689-694 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] 正城敏博,尾上孝雄,白川功,平田博章,木村浩三,浅原重夫,鷺島敬之: "“画像生成用多重スレッドプロセッサの高位合成手法による設計"" 第7回回路とシステム軽井沢ワークショップ. 61-66 (1994)

    • Related Report
      1994 Annual Research Report

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Published: 1994-04-01   Modified: 2016-04-21  

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