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Ultra-Highly-Parallel Arithmetic and Logic Circuits and Their Multiple-Valued Integration

Research Project

Project/Area Number 06452386
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionTohoku University, Graduate School of Information Sciences

Principal Investigator

KAMEYAMA Michitaka  Tohoku University, Graduate School of Information Sciences, Professor, 大学院情報科学研究科, 教授 (70124568)

Co-Investigator(Kenkyū-buntansha) HANYU Takahiro  Tohoku University, Graduate School of Information Sciences, Associate Professor, 大学院情報科学研究科, 助教授 (40192702)
Project Period (FY) 1994 – 1996
Project Status Completed (Fiscal Year 1996)
Budget Amount *help
¥5,800,000 (Direct Cost: ¥5,800,000)
Fiscal Year 1996: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 1995: ¥1,600,000 (Direct Cost: ¥1,600,000)
Fiscal Year 1994: ¥3,100,000 (Direct Cost: ¥3,100,000)
KeywordsHighly Parallel Arithmetic and Logic Circuit / Linear Digital Circuit / Reed-Muller Expansion / Critical-Path Minimization / Redundant Coding / Multiple-Valued Current-Mode Integrated Circuit / Low Power Multiple-Valued Integrated Circuit / 超高並列演算システム / 多値集積回路 / リ-ドマラ-展開 / 知能集積システム
Research Abstract

Highly parallel hardware algorithms based on new data representation and circuit technology are key issues to develop VLSI processors in deep submicron geometry. Local computability and parallelism are one of the most important factors to reduce the critical delay path which determines processor performance.
In this research project, multiple-valued redundant encoding method for parallel hardware algorithms were investigated together with the multiple-valued circuit technology. Our concept is that linearlity is fully utilized to make systematic design feasible. Linear combinational circuits are constructed by adders and coefficient multipliers over GF (p).
Let us assume that the specifications are given by symbol-level operations. A linear circuit for a unary operation can be always transformed to a highly parallel circuit whose output depends on only 2 input-digits by the matrix transformation called the similar transformation. If all representation matrices are equal each other in k-ar … More y operations, we can obtain consistent sparce matrices for K representation matrices. A symmetrical operation is such a class of operations. However, we cannot always linearize every k-ary specification. To solve the problem, we introduce multiplicated recundant symbols by assigning multiple-valued code vertices to one symbol. A sufficient condition for the symbol-level linearlity is derived to make the redundant multiple-valued code assignment.
Extension of the above design method is also discussed in a class of non-linear combinational circuits based on Reed-Muller expansion. If we can obtain a matrix representation of a combinational circuit with a formulation of the product of a constant matrix and variable vectors, design of a highly parallel circuit can be attributed to find a sparce constant matrix. Such class of the combinational circuits is more general, so it will be very useful for the design of practical k-ary operations such as an adder and a multiplier.
Another aspect of this research is low-power high performance multiple-valued integrated circuits. A new current-mode multiple-valued MOS integrated circuit is proposed with higher driving capability in comparison with the conventional binary and multiple-valued digital circuits. Moreover, an effective current-source control technique is found which leads to low-power high-speed multiple-valued threshold logic operations. This new circuit technology will be effectively employed for the highly parallel arithmetic and logic circuits developed in this project. Less

Report

(4 results)
  • 1996 Annual Research Report   Final Research Report Summary
  • 1995 Annual Research Report
  • 1994 Annual Research Report
  • Research Products

    (30 results)

All Other

All Publications (30 results)

  • [Publications] M.Nakajima: "Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k-Ary Operations" IEEE Proc.24th International Symposium on Multiple-Valued Logic. 223-230 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] 亀山 充隆: "キガスケールシステムオンチップに向けての知能集積システムの展望" 電子情報通信学会誌. 78. 187-194 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] M.Ryu: "Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices" IEEE Proc.25th International Symposium on Multiple-Valued Logic. 20-25 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] M.Nakajima: "Design of Highly Parallel Circuits Using EXOR Gates for Symmetrical Logic Operations" Proc.IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design. 308-313 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] T.Hanyu: "A 200 MHz Pipelined Multiplier Using 1.5 V-Supply Multiple-Valued MOS Current-Mode Circuits with Dual-Rail Source-Coupled Logic" IEEE Journal of Solid-State Circuits. 30. 1239-1245 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] M.Nakajima: "Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy" IEEE Proc. 26th International Symposium on Multiple-Valued Logic. 104-109 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] 中島 雅美: "シンボルレベル冗長性に基づく高並列線形演算回路の系統的設計" 電子情報通信学会誌. (掲載予定).

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] T.Hanyu: "Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control and Its Application" Proc.Asia and South Pacific Design Automation Conference 1997. 413-418 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] M.Nakajima and M.Kameyama: "Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k-Ary Operations" IEEE Proc.24th International Symposium on Multiple-Valued Logic.223-230 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] M.Ryu and M.Kameyama: "Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices" IEEE Proc.25th International Symposium on Multiple-Valued Logic.20-25 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] M.Nakajima and M.Kameyama: "Design of Highly Parallel Circuits Using EXOR Gates for Symmetrical Logic Operations" Proc.IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design. 308-313 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] T.Hanyu and M.Kameyama: "A 200 MHz Pipelined Multiplier Using 1.5 V-Supply Multiple-Valued MOS Current-Mode Circuits with Dual-Rail Source-Coupled Logic" IEEE Journal of Solid-State Circuits. Vol.30, No.11. (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] M.Nakajima and M.Kameyama: "Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy" IEEE Proc.26th International Symposium on Multiple-Valued Logic. 104-109 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] T.Hanyu, S.Kazama and M.Kameyama: "Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control and Its Application" Proc.Asia and South Pacific Design Automation Conference 1997. 413-418 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] M. Nakajima: "Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy" IEEE Proceeding 26th International Symposium on Multiple-Valued Logic. 104-109 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] 中島雅美: "2次形式リ-ドマラ-展開に基づく高並列演算回路の設計" 1996年電子情報通信学会ソサイエティ大会. A. A-51 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] 中島雅美: "シンボルレベル冗長性に基づく高並列演算回路の系統的設計" 電子情報通信学会誌. (掲載予定).

    • Related Report
      1996 Annual Research Report
  • [Publications] M.Ryu: "Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices" IEEE Proceedings 25th International Symposium on Multiple-Valued Logic. 20-25 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] M.Nakajima: "Design of Highly Parallel Circuits Using EXOR Gates for Symmetrical Logic Operations" Proceedings IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design. 308-313 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] 中島雅美: "線形性に基づく高並列対称演算回路の統一的設計" 1995年電子情報通信学会ソサイエティ大会. C-472. 194-194 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] M.Nakajima: "Design of Highly Parallel Linear Digital Circuits Based on a Symbol-Level Redundancy" IEEE Proceedings 26th International Symposium on Multiple-Valued Logic. (1996)

    • Related Report
      1995 Annual Research Report
  • [Publications] 中島雅美: "線形性に基づく対称多項演算回路の高並列化" 1996年電子情報通信学会総合大会. (1996)

    • Related Report
      1995 Annual Research Report
  • [Publications] M.Nakajima: "Design of Multiple-Valued Linear Digital Circuits for Highly Parallel κ-Ary Operations" IEEE Proceedings The Twenty-Fourth International Symposium on Multiple-Valued Logic. 223-230 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] 竜 盛博: "拡張化された表現行列に基づく高並列線形多項演算システムの設計" 多値論理研究ノート. 第17巻. 3-1-3-10 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] 渡辺充博: "分割理論と分枝限定法に基づく高並列演算回路の設計" 平成6年電気関係学会東北支部連合大会講演論文集. 2D2. 130-130 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] 竜 盛博: "スパース表現行列による高並列線形多項演算回路の設計" 平成6年電気関係学会東北支部連合大会講演論文集. 2D3. 131-131 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] 中島雅美: "高並列線形多項演算回路実現のための十分条件とその応用" 1994年電子情報通信学会秋季大会. D-80. 85-85 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] 亀山充隆: "知能集積システム用スーパーチップアーキテクチャ" 1994年電子情報通信学会秋季大会. GC-2-3. 255-256 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] T.Hanyu: "A 1.5V-Supply 200MHz Pipelined Multiplier Using Multiple-Valued Current-Mode MOS Differential Logic Circuits" 1995 IEEE International Solid-state Circuits Conference. FP19.2. 314-315 (1995)

    • Related Report
      1994 Annual Research Report
  • [Publications] 中島雅美: "対称演算仕様に対する高並列線形多項演算回路の設計" 1995年電子情報通信学会総合大会. D-139. (1995)

    • Related Report
      1994 Annual Research Report

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Published: 1994-04-01   Modified: 2016-04-21  

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