Fabrications of MOS device with a Stair-Shaped I-V Curves for Multiple-Valued Flip Flop
| Project/Area Number |
06555104
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| Research Category |
Grant-in-Aid for Developmental Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Miyagi National College of Technologi |
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Principal Investigator |
KARASAWA Shinji Miyagi National College of Technology, Dept. of Electrical Eng., Profssor, 電気工学科, 教授 (10042243)
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| Co-Investigator(Kenkyū-buntansha) |
OMORI Junichi NEC IC Microcomputer System Ltd. Dept. of Digital LSI Eng., Maneger, システムマイクロ第一技術部, 技術課長
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| Project Period (FY) |
1994 – 1995
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| Project Status |
Completed (Fiscal Year 1995)
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| Budget Amount *help |
¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 1995: ¥300,000 (Direct Cost: ¥300,000)
Fiscal Year 1994: ¥500,000 (Direct Cost: ¥500,000)
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| Keywords | MOSFET / punch-through / turn-on voltage / depletion layr / inversion layr / n‐MOSFET |
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| Research Abstract |
The stair-shaped I-V characteristics are obtained by inserting a stair-shaped gap between the gate and drain a metal-oxide-semiconductor field effect transis (MOSFET). The turn-on voltage depend on the amount of impurity ions along the path of punch-through. I-V characteristics of the poly silicon gate n-channel enhancement type MOS divide are complementary to those of the Al-gate p-channel MOS device with a similar structure. The stable step functional I-V characteristics are measured under a negative bias voltage applied to the substrate of boron deped p-Si.
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Report
(3 results)
Research Products
(7 results)
