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INTEGRATION OF NEURAL NETWORKS USING SUPERCONDUCTIVE DEVICES

Research Project

Project/Area Number 06555112
Research Category

Grant-in-Aid for Developmental Scientific Research (B)

Allocation TypeSingle-year Grants
Research Field System engineering
Research InstitutionTOHOKU UNIVERSITY

Principal Investigator

NAKAJIMA Koji  Research Inst. of Electrical Comm., Tohoku University Professor, 電気通信研究所, 教授 (60125622)

Co-Investigator(Kenkyū-buntansha) YAMASHITA Tsutomu  Research Inst. of Electrical Comm., Tohoku University Professor, 電気通信研究所, 教授 (30006259)
SAWADA Yasuji  Research Inst. of Electrical Comm., Tohoku University Professor, 電気通信研究所, 教授 (80028133)
Project Period (FY) 1994 – 1995
Project Status Completed (Fiscal Year 1995)
Budget Amount *help
¥8,000,000 (Direct Cost: ¥8,000,000)
Fiscal Year 1995: ¥3,100,000 (Direct Cost: ¥3,100,000)
Fiscal Year 1994: ¥4,900,000 (Direct Cost: ¥4,900,000)
KeywordsFluxon / Neural Network / Superconductor / Integrated Circuits / Variable Synapses / A / D Converter / Flux Quantum / SQUID / 時速量子
Research Abstract

We have designed and fabricated three types of Josephson integrated circuits ; a 3-bit neuron-based A/D converter, an RS flip-flop circuit, and extended phase-mode logic circuits.
The 3-bit neuron-based A/D converter comprises three neuron devices and three synapse devices which we have developed recently. The circuit has been integrated using a Nb/ AlOx/Nb junction process and tested with low-frequency analog input. We have presented the experimental operation in Appl. Phys. Lett. and IEEE Trans. Appl. Superconduct.
The RS flip-flop, which is designed for a memory device in superconducting neural networks, is composed of two superconducting neuron devices and two fixed synapse resistors. Numerical simulation results show its high speed operation up to 50GHz, which we have presented in IEICE Trans. Electron. Experimental results have been submitted to IEEE Trans. Appl. Superconduct.
The extended phase-mode logic (EPL) circuits are designed for control units in superconducting neural networks. The EPL circuits utilizes a single-flux-quantum as an information bit. Test results for an INHIBIT gate, which is one of universal operations in terms of Boolean algebra, has been published in IEEE Trans. Appl. Superconduct. Test results for a binaly counter circuit has been submitted to IEICE Trans. Electron.

Report

(3 results)
  • 1995 Annual Research Report   Final Research Report Summary
  • 1994 Annual Research Report
  • Research Products

    (24 results)

All Other

All Publications (24 results)

  • [Publications] Y. Mizugaki et. al: "Implementation of superconducting synapse into a neuron-based analog-to-digital converter" Appl Phys. Lett.65. 1712-1713 (1994)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] S. Sato et. al: "LSI Neural Chip of Pulse-Output Network with Programmable Synapse" IEICE Trans. Electron.E78-C. 94-100 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] K. Nakajima et. al: "Hardware Implementation of New Analog Memory for Neural Networks" IEICE Trans. Electron.E78-C. 101-105 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] Y. Mizugaki et. al: "Neuro-Base Josephson Flip-Flop" IEICE Trans. Electron.E78-C. 531-534 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] Y. Mizugaki et. al: "Superconducting Neural Circuits Using SQUID_s" IEEE Trans. Appl. Superconduct.22GD05:5. 3168-3171 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] T. Onomi et. al: "Extended Phase-Mode Logic-Circuits with Resistive Ground Contact" IEEE Trans. Appl. Superconduct.5. 3464-3471 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] MIZUGAKI,Yoshinao et. al: "Implementation of superconducting synapse into a neurobased analog-to-digital converter" Appl. Phys. Lett.vol.65. 1712-1713 (1994)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] SATO,Shigeo et. al: "LSI Neural Chip of Pulse-Output Network with Programmable Synapse" IEICE Trans. Electron.vol.E78-C. 94-100 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] NAKAJIMA,Koji et. al: "Hardware Implementation of New Analog Memory for Neural Networks" IEICE Trans. Electron.vol. E78-C. 101-105 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] MIZUGAKI,Yoshinao et. al: "Neuro-Base Josephson Flip-Flop" IEICE Trans. Electron.vol. E78-C. 531-534 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] MIZUGAKI,Yoshinao et. al: "Superconducting Neural Circuits Using SQUIDs" IEEE Trans. Appl. Superconduct. vol. 5. 3168-3171 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] ONOMI,Takeshi et. al: "Extended Phase-Mode Logic-Circuits with Resistive Ground Contact." IEEE Trans. Appl. Superconduct. vol. 5. 3464-3471 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] Y.Mizugaki et.al: "Implementation of superconducting synapse into a neuro-based analog-to-digital converter" Appl.Phys.Lett.65. 1712-1713 (1994)

    • Related Report
      1995 Annual Research Report
  • [Publications] S.Sato et.al: " LSI Neural Chip of Pulse-Output Network with Programmable Synapse" IEICE Trans.Electron.E78-C. 94-100 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] K.Nakajima et.al: "Hardware Implementation of New Analog Memory for Neural Networks" IEICE Trans.Electron.E78-C. 101-105 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] Y.Mizugaki et.al: "Neuro-Base Josephson Flip-Flop" IEICE Trans.Electron.E78-C. 531-534 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] Y.Mizugaki et.al: "Superconducting Neural Circuits Using SQUIDs" IEEE Trans.Appl.Superconduct.5. 3168-3171 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] T.Onomi et.al: "Extended Phase-Mode Logic-Circuits with Resistive Ground Contact" IEEE Trans.Appl.Superconduct.5. 3464-3471 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] Y.Sawada: "A scaling theory of living state" Phisyca A. 204. 543-554 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] Y.Mizugaki: "Implementation of supercpnducting synapse into a neuro-based analog-to-digital converter" Appl.Phys.Lett.65. 1712-1713 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] H.Won: "A Pulsating Neural Network" Extended Abstracts of the 1994 Int.Conf.on SSDM. 379-381 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] Y.Mizugaki: "New Approach Implementation of Neural Circuits Using Superconductive Devices" Extended Abstracts of the 1994 Int.Conf.on SSDM. 364-366 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] S.Sato: "LSI Neural of Chip Pulse-Output Network with Programmable Synapse" IEICE Trans.ELECTRON.E78-C. 94-100 (1995)

    • Related Report
      1994 Annual Research Report
  • [Publications] K.Nakajima: "Hardware Implementation of New Analog Memory for Neural Networks" IEICE Trans.ELECTRON.E78-C. 101-105 (1995)

    • Related Report
      1994 Annual Research Report

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Published: 1994-04-01   Modified: 2016-04-21  

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