Project/Area Number |
06650357
|
Research Category |
Grant-in-Aid for General Scientific Research (C)
|
Allocation Type | Single-year Grants |
Research Field |
Electronic materials/Electric materials
|
Research Institution | University of Electro-Communications. |
Principal Investigator |
KOBAYASHI Tadayuki University of Electro-Communications, Dept.of Electro-Communications, Professor., 電気通信学部, 教授 (00123969)
|
Co-Investigator(Kenkyū-buntansha) |
GOTO Toshinari University of Electro-Communications, Dept.of Electro-Communications, Professor., 電気通信学部, 教授 (70017333)
|
Project Period (FY) |
1994 – 1995
|
Project Status |
Completed (Fiscal Year 1995)
|
Budget Amount *help |
¥2,100,000 (Direct Cost: ¥2,100,000)
Fiscal Year 1995: ¥600,000 (Direct Cost: ¥600,000)
Fiscal Year 1994: ¥1,500,000 (Direct Cost: ¥1,500,000)
|
Keywords | High Tc superconductor / Thin film / sputtering / Tunnel junction / 超伝導酸化物薄膜 / a軸配向膜 |
Research Abstract |
Sandwich type SIN junctions of YBa<@D22@>D2Cu<@D23@>D2Ox(YBCO)/SrTiO<@D23@>D2(STO)/Au and YBCO/PrGaO<@D23@>D2(PGO)/Au were fabricated using a-axis oriented YBCO films under the some conditions using a rf magnetron sputtering with dc voltage biased substrate holder. The differential conductance-voltage(dI/dV-V) curves of junctions with defferent barrier thickness were investigated. The junction showed the tunnel-like behavior, though some junctions showed the curves with pinhole-short-circuits. The junctions had the change in the gradient of differential conductance in the curves at about (]SY.+-。[) 20mV.This change was obviously observed with decreasing the barrier thickness. On the other hand, it was also observed the small zero bias anomalies for the junctions with thin barrier. The curves of junctions with PGO barrier were simillar to those with the STO barrier. It is considered that the tunneling occurs via thin region in the ununiform barrier. And then, the effects of dI/dV-V curves on the heat treatment in oxygen gas were also investigated. In order to obtain the change in the gradient of dI/dV in the dI/dV-V curve, the optimum annealing time was 2-4h. The slope of the background conductance of junctions becomes steep with increasing the annealing time.
|