| Budget Amount *help |
¥2,000,000 (Direct Cost: ¥2,000,000)
Fiscal Year 1995: ¥900,000 (Direct Cost: ¥900,000)
Fiscal Year 1994: ¥1,100,000 (Direct Cost: ¥1,100,000)
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| Research Abstract |
Becase the gray and colored images have multiple levels, a multiple-valued logic system for picture processing is more effective as compared with a binary logic system.
We propese several operations and report ternary digital picture processing sircuits (TDPPC's). The TDPPC's consist of ternary/binary level converters, binary/ternary level converters, ternary comparators, neighborhood operation circuits, ternary half adders and center pixel output circuit. Algorithms for noise reduction, border line extraction, logic difference, thinning, and connected component extraction on ternary logic are used in the developments and designs of the TDPPC's. Moreover, we construct a basic system including a host personal computer. TDPPC's utilized in this system are verified by the algorithms.
Further, we examine border extraction with Laplatian-Gaussian filter by ternary method, extracting image contours for full color image by using multi-valued processing with Hue・Saturation・Light (HSL), and improvement of printing for digital picture. In extracting region system, becase the histogram processing can be adapted for hue and saturation in addition to light, we used a multiple-valued output system combined hue and light, or hue and saturation. Therefore, we examine to extract the appropriate state of original picture at once.
Moreover, we examine ternary fundamental operation circuits which are compositions for circuits, and realized ternary picture processing circuits in voltage-mode. And we examine bidirectional current-mode circuits. Those ternary picture processing circuits are expected speeding up by paraller processing. The results have been published in papers and conferences.
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