| Budget Amount *help |
¥1,400,000 (Direct Cost: ¥1,400,000)
Fiscal Year 1995: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 1994: ¥900,000 (Direct Cost: ¥900,000)
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| Research Abstract |
We proposed and implemented a prototype of the variable parallelism scheduler for multithreaded computers on a simulator. Using small scale application programs, we first study on behavior of working ratio of processing unit in the multithreaded processor. Performance analysis under condition with dynamic active thread number control is done. It leads effectiveness of dynamic control method. And, we proposed an effective calculation method for working ratio of processing unit from the processor structure model and system parameters (such as number of pipeline stages, memory access delay and cache miss ratio). By simulation, correctness and effectiveness of this method are confirmed.
We also discussed on conditions which enable the effective processing with fully utilazation of limited size of on-chip cache, especially performance impact with respect to problem siza. As result, we show importance of an processor system parameter estimation method, which calculates them from execution time data of intentionally synthesized programs ( tuned to be sensitive to typical system parameters ) in single processor environment.
To generalize the problem, about what called scalability, we redefine this index of achieved performance, as a function of system size and problem size. We propose new method to find better "working point" to avoid bettlenecks determined by specific parameter of each system element. Then we can us this function to estimate performances under various conditions. By this method, we first calculate system parameters from performances measured on small scale system, then we ca estimate performances on large scale system. Experiments on parallel computers and workstation cluster show effectiveness of this method.
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