Simultaneous Circuit and Layout Design Method for Analog LSIs under Performance Constraints
| Project/Area Number |
06680317
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機科学
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| Research Institution | KYOTO UNIVERSITY |
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Principal Investigator |
ONODERA Hidetoshi Kyoto University, Graduate School of Engineering, Associate Professor, 工学研究科, 助教授 (80160927)
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| Co-Investigator(Kenkyū-buntansha) |
KOBAYASHI Kazutoshi Kyoto University, Graduate School of Engineering, Instructor, 工学研究科, 助手 (70252476)
VASILY Moshnyaga Kyoto University, Graduate School of Engineering, Lecturer, 工学研究科, 講師 (40243050)
TAMARU Keikichi Kyoto University, Graduate School of Engineering, Professor, 工学研究科, 教授 (10127102)
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| Project Period (FY) |
1994 – 1995
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| Project Status |
Completed (Fiscal Year 1995)
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| Budget Amount *help |
¥2,200,000 (Direct Cost: ¥2,200,000)
Fiscal Year 1995: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 1994: ¥1,100,000 (Direct Cost: ¥1,100,000)
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| Keywords | Analog Circuit / Analog Layout / Optimization / Layout Design / Circuit Design / Analog CAD / Analog HDL |
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| Research Abstract |
We have developed an efficient design method for analog LSIs which performs simultaneous circuit and layout design with explicit consideration of performance constraints. The method is realized by three key technologies ; symbolic layout technique for layout recycling, performance driven automatic layout, and performance optimization technique according to stored design procedures.
Our achievements are summarized as follows.
1. Development of symbolic layout technique for layout recycling
We have developed a symbolic layout technique that can update device shapes without design rule violation. The method can further optimize device shapes when they have multiple shape possibilities, so that overall layout space is minimized. This technique enables us to recycle previously designed layout for accommodating new performance specifications.
2. Development of performance driven layout methods.
In this project, we have devised a performance driven global routing method. The method treats all the nets simultaneously in every routing channel so that net ordering problem can be eliminated and globally optimized routing paths can be found. A concept of "routing possibility" and a resistor array model enable the simultaneous consideration.
3. Development of a performance optimization technique which utilizes stored design procedures Design parameters are optimized according to design procedures which are acquired from a design process of a designer. A new design variable called an "uncertainty parameter" is introduced in order to describe a design procedure with less confidence. In case the optimization process fails, the system automatically modifies the uncertainty parameter so that the design process can continue.
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Report
(3 results)
Research Products
(9 results)
