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Simultaneous Circuit and Layout Design Method for Analog LSIs under Performance Constraints

Research Project

Project/Area Number 06680317
Research Category

Grant-in-Aid for General Scientific Research (C)

Allocation TypeSingle-year Grants
Research Field 計算機科学
Research InstitutionKYOTO UNIVERSITY

Principal Investigator

ONODERA Hidetoshi  Kyoto University, Graduate School of Engineering, Associate Professor, 工学研究科, 助教授 (80160927)

Co-Investigator(Kenkyū-buntansha) KOBAYASHI Kazutoshi  Kyoto University, Graduate School of Engineering, Instructor, 工学研究科, 助手 (70252476)
VASILY Moshnyaga  Kyoto University, Graduate School of Engineering, Lecturer, 工学研究科, 講師 (40243050)
TAMARU Keikichi  Kyoto University, Graduate School of Engineering, Professor, 工学研究科, 教授 (10127102)
Project Period (FY) 1994 – 1995
Project Status Completed (Fiscal Year 1995)
Budget Amount *help
¥2,200,000 (Direct Cost: ¥2,200,000)
Fiscal Year 1995: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 1994: ¥1,100,000 (Direct Cost: ¥1,100,000)
KeywordsAnalog Circuit / Analog Layout / Optimization / Layout Design / Circuit Design / Analog CAD / Analog HDL
Research Abstract

We have developed an efficient design method for analog LSIs which performs simultaneous circuit and layout design with explicit consideration of performance constraints. The method is realized by three key technologies ; symbolic layout technique for layout recycling, performance driven automatic layout, and performance optimization technique according to stored design procedures.
Our achievements are summarized as follows.
1. Development of symbolic layout technique for layout recycling
We have developed a symbolic layout technique that can update device shapes without design rule violation. The method can further optimize device shapes when they have multiple shape possibilities, so that overall layout space is minimized. This technique enables us to recycle previously designed layout for accommodating new performance specifications.
2. Development of performance driven layout methods.
In this project, we have devised a performance driven global routing method. The method treats all the nets simultaneously in every routing channel so that net ordering problem can be eliminated and globally optimized routing paths can be found. A concept of "routing possibility" and a resistor array model enable the simultaneous consideration.
3. Development of a performance optimization technique which utilizes stored design procedures Design parameters are optimized according to design procedures which are acquired from a design process of a designer. A new design variable called an "uncertainty parameter" is introduced in order to describe a design procedure with less confidence. In case the optimization process fails, the system automatically modifies the uncertainty parameter so that the design process can continue.

Report

(3 results)
  • 1995 Annual Research Report   Final Research Report Summary
  • 1994 Annual Research Report
  • Research Products

    (9 results)

All Other

All Publications (9 results)

  • [Publications] H. Onodera: "Grobal Routing Algorithm for Analog Circuits Using a Resistor Array Model" Proc. IEEE ISCAS発表予定. (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] H. Onodera: "Development of Module Generators from Extracted Design Procedures" IEICE Trans. Fundamentals. E78-A. 160-168 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] H. Onodera: "Compaction with Shape Optimization and its Application to Layout Recycling" IEICE Trans. Fundamentals. E78-A. 169-176 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] H.Onodera: "Global Routing Algorithm for Analog Circuits Using a Resistor Array Model" Proc.IEEE ISCAS. (to appear). (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] H.Onodera: "Development of Module Generators from Extracted Design Procedures" IEICE Trans. Fundamentals. Vol.E78-A. 160-168 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] H.Onodera: "Compaction with Shape Optimization and its Application to Layout Recycling" IEICE Trans. Fundamentals. Vol.E78-A. 169-176 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1995 Final Research Report Summary
  • [Publications] H. Onodera: "Grobal Routing Algorithm for Analog Circuits Using a Resistor Array Model" Proc. IEEE ISCAS発表予定. (1996)

    • Related Report
      1995 Annual Research Report
  • [Publications] H.Onodera: "Compaction with Shape Optimization" Proc.IEEE CICC. 545-548 (1994)

    • Related Report
      1994 Annual Research Report
  • [Publications] H.Onodera: "Compaction with Shape Optimization and its Application to Layout Recycling" IEICE Trans.Fundamentals. E78-A. 169-176 (1995)

    • Related Report
      1994 Annual Research Report

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Published: 1994-04-01   Modified: 2016-04-21  

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