Study on Neutron Damage Dynamics of Semiconductor Crystal
| Project/Area Number |
06680469
|
|---|
| Research Category |
Grant-in-Aid for General Scientific Research (C)
|
| Allocation Type | Single-year Grants |
|---|
| Research Field |
エネルギー学一般・原子力学
|
|---|
| Research Institution | Osaka University |
|---|
Principal Investigator |
IIDA Toshiyuki Osaka University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (60115988)
|
|---|
| Project Period (FY) |
1994 – 1995
|
| Project Status |
Completed (Fiscal Year 1995)
|
| Budget Amount *help |
¥1,900,000 (Direct Cost: ¥1,900,000)
Fiscal Year 1995: ¥900,000 (Direct Cost: ¥900,000)
Fiscal Year 1994: ¥1,000,000 (Direct Cost: ¥1,000,000)
|
|---|
| Keywords | Si-SBD / Neutron Displacement Damage / CMOS SRAM IC / DT・DD Neutron Damage Correlation / TRIM-90 / Si (n, alpha) Mg Reaction / Neutron-induced Soft-error / Bit Soft-error Cross Section / アクセプター型欠陥 / Zheng Liモデル / 電子捕獲中心 / コール・コール円弧則 / 有極性液体 / 配向分極 / 照射効果ダイナミクス / 原子弾き出し / DT・DD中性子損傷相関係数 / 荷電粒子輸送コードTRIM |
|---|
| Research Abstract |
A silicon surface barrier detector (Si-SBD) was irradiated with fusion neutrons from a deuteron accelerator. The leakage current of the detector increased proportionally with neutron fluence, which determined the neutron damage constant for the Si-SBD.The correlation factor of the DT and DD neutron damage in the Si-SBD was determined from the ratio of the DT and DD neutron damage constants and was found to be 2.3. We also calculated the rate of DT and DD neutron displacement damage for Si by using the ion transport code TRIM-90 and data on neutron reactions in the Si-SBD.The correlation factor of DT and DD neutron damage from the calculation agreed with that from the Si-SBD irradiation experiment.
In order to examine the neutron induced soft-error on memory ICs, several kinds of 1 Mbit CMOS SRAM ICs were irradiated with 14 MeV neutrons. Considering the cell population in the chip, we obtained the neutron susceptibility constant, i.e. bit softerror cross section of 6-9*10^<-14> cm^2 for 1 Mbit CMOS SRAM ICs. This means that a soft-error is caused by neutron reactions in a limited region in a memory cell. The bit soft-error cross section value agreed roughly with that calculated by computer simulation with a Monte Carlo program based on the TRIM-90 code and the ENDF/B-VI neutron cross section data.
|
Report
(3 results)
Research Products
(7 results)
