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A high performance on-chip data transfer technique using pulse modulation signals

Research Project

Project/Area Number 07455151
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 電子デバイス・機器工学
Research InstitutionHIROSHIMA UNIVERSITY

Principal Investigator

IWATA Atsushi  HIROSHIMA UNIVERSITY,FACULTY OF ENGINEERING,PROFESSOR, 工学部, 教授 (30263734)

Co-Investigator(Kenkyū-buntansha) YOKOYAMA Shin  HIROSHIMA UNIVERSITY,NANO-DEVICE SYSTEM RESEARCH CENTER,PROFESSOR, ナノデバイス・システム研究センター, 教授 (80144880)
Project Period (FY) 1995 – 1996
Project Status Completed (Fiscal Year 1996)
Budget Amount *help
¥7,200,000 (Direct Cost: ¥7,200,000)
Fiscal Year 1996: ¥3,400,000 (Direct Cost: ¥3,400,000)
Fiscal Year 1995: ¥3,800,000 (Direct Cost: ¥3,800,000)
KeywordsPULSE MODULATION / PULSE WIDTH MODULATION / PULSE PHASE MODULATION / DATA TRANSFER / CMOS TECHNOLOGY / TRANSCEIVER CIRCUIT / GATE ARRAY / 回路設計 / 位相検出回路 / 位相同期回路 / 変復調回路
Research Abstract

In order to improve a bit rate and power efficiency for on-chip data transfer systems, data transceiver circuits using pulse modulation signals were developed. A pulse phase modulation (PPM) system has higher performance comparing with a pulse width modulation (PWM). However, PPM requires precision phase synchronizing circuit which consumes much power and chip area. A PWM data transceiver circuits were designed by using a 250-MHz, 4-phase delay locked loop technique, and a 1ns time resolution was obtained. It realizes 1Gbits/sec data rate with low power dissipation. For implementations by gate arrays, a PWM transceiver circuit utilizing only logic gates was developed. These transceiver circuits were described by hardware description language (HDL), and synthesized by logic synthesis tools. The circuits were evaluated by logic simulation (Verilog-XL) and circuits simulation (HSPICE). The PWM transceiver test chip was designed using a 0.5mum CMOS process. A Mask Layout was designed by standard cell design tools. A measurement technique for a 1ns timing accuracy and a bit error rate of the PWM transceiver was achieved using an arbitrary wave from generator and a logic analyzer. The measurements results of the test chip shows that maximum clock frequency and timing accuracy are almost as the same as the simulation results.

Report

(3 results)
  • 1996 Annual Research Report   Final Research Report Summary
  • 1995 Annual Research Report
  • Research Products

    (21 results)

All Other

All Publications (21 results)

  • [Publications] 永田・米田・岩田: "PWM信号処理回路とコホ-ネンネットワークへの応用" 信学技報・集積回路(ICD-95). 10. 71-78 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] A.Iwata and M.Nagata: "A Concept of Analog-Digital Merged Circuit Architecture for Future VLSI's" IEICE Trans.Fundamentals(Vol.E79-A). No.2. 145-157 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] 米田・岩田・他5名: "パルス幅変調信号距離演算回路の設計" DAシンポジウム '96. 8月号. 25-30 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] 岩田・永田: "アナログ・ディジタル融合新アーキテクチャ" 信学技報・集積回路(ICD-96). 114. 31-38 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] A.Iwata and M.Nagata: "A Concept of Analog-Digital Merged Circuit Architecture for Future VLSI's" International Journal of Analog IC and Signal Processing. Vol.11-2. 83-96 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] M.Nagata and A.Iwata: "A minimum Distance Search Circuit using Dual-Line PWM Signal Processing and Charge Packet Counting Techniques" ISSCC Digest of Technical Papers. Vol.40. 42-43 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] M.Nagata, N.Yoneda and A.Iwata: "Pulse Width Modulation based signal processing circuits and its application for Kohonen Network" Technical report of IEICE. ICD95-10, CPSY95-10, FTS95-10. 71-78 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] A.Iwata and M.Nagata: "A Concept of Analog-Digital merged Circuit Architecture for Future VLSI's" IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences. Vol.E79-A,No.2. 145-157 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] N.Yoneda, A.Iwata, et.al.: "A.LSI design of the Manhattan distance calculation processor using Pulse Width Modulation" DA symposium '96. Aug.25-30 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] A.Iwata and M.Nagata: "A Novel Architecture using Analog-Digital merged Circuits" TECHNICAL REPORT OF IEICE. ICD96-114. 31-38 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] A.Iwata and M.Nagata: "A Concept of Analog-Digital merged Circuit Architecture for Future VLSI's" International Journal of Analog Integrated Circuits and Signal Processing. Vol.11, No.2. 83-96 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] M.Nagata, A.Iwata, et.al.: "A minimum Distance Search Circuit using Dual-Line PWM Signal Processing and Charge Packet Counting Techniques" ISSCC Digest of Technical Paters. Vol.40. 42-43 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1996 Final Research Report Summary
  • [Publications] 永田・米田・岩田: "PWN信号処理回路とコホ-ネンネットワークへの応用" 信学技報・集積回路(ICD-95). 10. 71-78 (1995)

    • Related Report
      1996 Annual Research Report
  • [Publications] A. Iwata and M. Nagata: "A Concept of Analog-Digital Merged Circuit Architecture for Future VLSI's" IEICE Trans. Fundamentals (Vol. E79-A). No. 2. 145-157 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] 米田・岩田・他5名: "パルス幅変調信号距離演算回路の設計" DAシンポジウム '96. 8月号. 25-30 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] 岩田・永田: "アナログ・ディジタル融合新アーキテクチャ" 信学技報・集積回路(ICD-96). 114. 31-38 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] A. Iwata and M. Nagata: "A Concept of Analog-Digital Merged Circuit Architecture for Future VLSI's" International Journal of Analog IC and Signal Processing. Vol. 11-2. 83-96 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] M. Nagata and A. Iwata: "A minimum Distance Search Circuit using Dual-Line PWM Signal Processing and Charge Packet Counting Techniques" ISSCC Digest of Technical Papers. Vol, 40. 42-43 (1997)

    • Related Report
      1996 Annual Research Report
  • [Publications] 岩田 穆: "アナログ・デジタル融合回路アーキテクチャ" 電子情報通信学会エレクトロニクスソサイエティ大会. 2. 289-290 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] 岩田 穆: "可変遅延回路不要なPWM信号受信回路" 1996年電子情報通信学会総合大会. (印刷中). (1996)

    • Related Report
      1995 Annual Research Report
  • [Publications] 岩田 穆: "4相クロックを用いたPWM-Binary Digital 相互変換回路" 1996年電子情報通信学会総合大会. (印刷中). (1996)

    • Related Report
      1995 Annual Research Report

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Published: 1995-04-01   Modified: 2016-04-21  

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