| Project/Area Number |
07458052
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | University of Tokyo |
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Principal Investigator |
TANAKA Hidehiko The University of Tokyo, Graduate School of Engineering, 大学院・工学系研究科, 教授 (60011102)
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| Project Period (FY) |
1995 – 1997
|
| Project Status |
Completed (Fiscal Year 1997)
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| Budget Amount *help |
¥6,800,000 (Direct Cost: ¥6,800,000)
Fiscal Year 1997: ¥1,000,000 (Direct Cost: ¥1,000,000)
Fiscal Year 1996: ¥1,800,000 (Direct Cost: ¥1,800,000)
Fiscal Year 1995: ¥4,000,000 (Direct Cost: ¥4,000,000)
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| Keywords | dataflow anaysis / VLDP / branch handling / speculative execution / dynamic prefetch / address prediction / data traffic / ILP / VLDP / 大規模データパスプロセッサ / 分岐予測 / 並列度 / タイム管理モジュール / 処理ステップオ-ガナイザ / マッピングモジュール / データフロー変換 / メモリアロケイタ |
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| Research Abstract |
In this research, we took a close look at parallelism extraction, handling of control dependencies, and enhanced memory system, which could be the key technologies of Very Large Data Path (VLDP) architecture. The outcome we gained are as follows.
Firstly, we examined the characteristics of parallelism restricted by control dependencies and data dependencies : we found that the VLDP architecture can achieve dozens of times as much performance as conventional scalar processors can, when we have both the perfect branch predictor and the complete memory system.
Secondly, we examined suitable branch handling for the VLDP architecture. This branch handling needs to treat simultaneously plural control flow and needs to fetch instructions speculatively across many branches. For this purpose, we proposed a new branch predictor named multi-level branch predictor and examined its behavior.
Thirdly, we improved a memory system based on the cache mechanism by utilizing a newly proposed data prefetch algorithm that predicts a referenced address based on the evaluation of a linear function. We confirmed this new system lessens overhead of memory references. Moreover we examined the traffic between the memory and the datapath, which tends to be a bottleneck for high performance processors. We showed that this traffic is reduced to less than half of conventional scheme when the VLDP architecture utilizes the direct data transfer among the remarkable number of ALUs.
From these results, technological issues of VLDP architecture are made clear and we confirmed the possibility of performance improvement.
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