| Project/Area Number |
07458060
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Nara Institute of Science and Technology |
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Principal Investigator |
WATANABE Katsumasa Nara Institute of Science and Technology, Graduate School of Information Science, Professor, 情報科学研究科, 教授 (60026078)
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| Co-Investigator(Kenkyū-buntansha) |
TAKAGI Kazuyoshi Nara Institute of Science and Technology, Graduate School of Information Science, 情報科学研究科, 助手 (70273844)
KUNISHIMA Takeo Okayama Prefectural University, Faculty of Computer Science and System Engineeri, 情報工学部, 助手 (20263436)
KIMURA Shinji Nara Institute of Science and Technology, Graduate School of Information Science, 情報科学研究科, 助教授 (20183303)
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| Project Period (FY) |
1995 – 1997
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| Project Status |
Completed (Fiscal Year 1997)
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| Budget Amount *help |
¥5,800,000 (Direct Cost: ¥5,800,000)
Fiscal Year 1997: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 1996: ¥1,600,000 (Direct Cost: ¥1,600,000)
Fiscal Year 1995: ¥3,500,000 (Direct Cost: ¥3,500,000)
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| Keywords | Hardware / Software Codesign / Software Co-operation / High Level Synthesis / Reconfigurable System / Hardware Accelerator / Field Programmable Gate Array (FPGA) / General Purpose Co-processor / C compiler / 汎用コブロセッサ / ソフトウェア協調設計 / ハードウェア記述言語 / 並列化コンパイラ / コデザイン / エミュレーション / コプロセッサ / 論理合成 |
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| Research Abstract |
We have investigated computer systems with reconfigurable general purpose co-processors, and the hardware/software codesign environment for the systems. The results of our research are as follows :
1. We have proposed a reconfigurable coprocessor architecture made of FPGAs (Field Programmable Gate Arrays), a cache memory, and a bus interface.
2. We have designed and implemented a prototype of the co-processor for Sun workstations. The coprocessor includes 4 FPGAs, a 1 MB cache memory, and a bus interface with a hardware queue.
3. We proposed a hardware/software codesign environment for the computer system with the co-processor. We have investigated the system description languages and the co-operation method between the main processor and the co-processor.
4. We have designed and implemented the codesign environment from C programs for the coprocessor system. The hardware/software codesign compiler accepts a C program and estimates the execution time and the hardware costs of each function
… More
when the function is implemented as a hardware. The compiler also estimates the execution time of the function with the software implementation. Then the compiler decides the implementation method of each function.
5. We have investigated the optimization method of C programs to be implemented as hardware modules on FPGAs. We have introduced hardware independent optimization methods such as the loop-unrolling, the variable bit-length reduction, the function expansion, ets., optimization methods such as the 4-1 LUT (Look-Up Table) based hardware estimation method, the marge method of bit-level operations, etc.
6. We have tested several algorithms on the prototype of the codesign system, which include lexical analysis, sorting, and several graphic applications. We have found that the FPGA based co-processor is useful for the fast execution of programs, when the program include the parallel-if structure or the bit-level operations.
In the future, we would like to investigate context switching on the co-preoessor system, and dynamic reconfigurability of the co-processor. Less
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