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Research on Reconfigurable General Purpose Co-processor Systems and Their Optimized Hardware/Software Codesign Compiler

Research Project

Project/Area Number 07458060
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionNara Institute of Science and Technology

Principal Investigator

WATANABE Katsumasa  Nara Institute of Science and Technology, Graduate School of Information Science, Professor, 情報科学研究科, 教授 (60026078)

Co-Investigator(Kenkyū-buntansha) TAKAGI Kazuyoshi  Nara Institute of Science and Technology, Graduate School of Information Science, 情報科学研究科, 助手 (70273844)
KUNISHIMA Takeo  Okayama Prefectural University, Faculty of Computer Science and System Engineeri, 情報工学部, 助手 (20263436)
KIMURA Shinji  Nara Institute of Science and Technology, Graduate School of Information Science, 情報科学研究科, 助教授 (20183303)
Project Period (FY) 1995 – 1997
Project Status Completed (Fiscal Year 1997)
Budget Amount *help
¥5,800,000 (Direct Cost: ¥5,800,000)
Fiscal Year 1997: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 1996: ¥1,600,000 (Direct Cost: ¥1,600,000)
Fiscal Year 1995: ¥3,500,000 (Direct Cost: ¥3,500,000)
KeywordsHardware / Software Codesign / Software Co-operation / High Level Synthesis / Reconfigurable System / Hardware Accelerator / Field Programmable Gate Array (FPGA) / General Purpose Co-processor / C compiler / 汎用コブロセッサ / ソフトウェア協調設計 / ハードウェア記述言語 / 並列化コンパイラ / コデザイン / エミュレーション / コプロセッサ / 論理合成
Research Abstract

We have investigated computer systems with reconfigurable general purpose co-processors, and the hardware/software codesign environment for the systems. The results of our research are as follows :
1. We have proposed a reconfigurable coprocessor architecture made of FPGAs (Field Programmable Gate Arrays), a cache memory, and a bus interface.
2. We have designed and implemented a prototype of the co-processor for Sun workstations. The coprocessor includes 4 FPGAs, a 1 MB cache memory, and a bus interface with a hardware queue.
3. We proposed a hardware/software codesign environment for the computer system with the co-processor. We have investigated the system description languages and the co-operation method between the main processor and the co-processor.
4. We have designed and implemented the codesign environment from C programs for the coprocessor system. The hardware/software codesign compiler accepts a C program and estimates the execution time and the hardware costs of each function … More when the function is implemented as a hardware. The compiler also estimates the execution time of the function with the software implementation. Then the compiler decides the implementation method of each function.
5. We have investigated the optimization method of C programs to be implemented as hardware modules on FPGAs. We have introduced hardware independent optimization methods such as the loop-unrolling, the variable bit-length reduction, the function expansion, ets., optimization methods such as the 4-1 LUT (Look-Up Table) based hardware estimation method, the marge method of bit-level operations, etc.
6. We have tested several algorithms on the prototype of the codesign system, which include lexical analysis, sorting, and several graphic applications. We have found that the FPGA based co-processor is useful for the fast execution of programs, when the program include the parallel-if structure or the bit-level operations.
In the future, we would like to investigate context switching on the co-preoessor system, and dynamic reconfigurability of the co-processor. Less

Report

(4 results)
  • 1997 Annual Research Report   Final Research Report Summary
  • 1996 Annual Research Report
  • 1995 Annual Research Report
  • Research Products

    (29 results)

All Other

All Publications (29 results)

  • [Publications] 木村 晋二: "Residue BDD and Its Application to the veripication of Arithmetic Circuits" 32nd Design Automation Conference. 542-545 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] 伊藤 康史, 平尾 誠, 木村 晋二, 渡邊 勝正: "汎用コプロセッサGPCP-SSの実現と評価" 電子情報通信学会VLD研究会. VLDG5-89 (FTS95-62). 87-94 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] 雪下充 輝, 名古屋 彰, 伊藤 康史, 木村 晋二: "ハードウェア/ソフトウェア協調動作システム" 情報処理学会DA研究会. 78-21. 127-132 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] 伊藤 康史, 平尾 誠, 木村 晋二, 渡邊 勝正: "汎用コプロセッサGPCP-SSのハードウェア/ソフトウェア協調設計のためのコンパイラ" DAシンポジウム′96論文集. 123-128 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] 木村 晋二, 雪下充 輝, 伊藤 康史, 名古屋 彰, 平尾 誠, 渡邊 勝正: "A Hardware/Software Codesign Method for a General Purpose Reconfigureble Coproceser" 5th International Workshop on Hardware/Software Codesign. 147-151 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] 中村 一博, 木村 晋二, 高木 一義, 渡邊 勝正: "順序回路の待ち状態に起因するフォールスパスの解析手法" 電子情報通信学会 VLD研究会. (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Shinji Kimura: "Residue BDDand Its Application to the Verification of Arithmetic Circuits" Proc.32bd Design Automation Conference. 542-545 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Shinji Kimura: "Design Verification of Arithmetic Circuits Using Residue BBD's (in Japanese)" Technical Reports of IEICE. VLD95-46. 1-8 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Futoshi Matsumoto, Shinji Kimura and Katsumasa Watanabe: "A Parallel Transduction Method using Parallel BDD Manipulation (in Japanese)" Technical Report of IEICE. VLD95-89. 1-8 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Yasufumi Itoh, Makoto Hirao, Shinji Kimura and Katsumasa Watanabe: "Design and Implementation of Reconfigurable General Purpose Coprocessor GPCP-SS (in Japanese)" Technical Report of IEICE. VLD95-100/FTS95-62. 87-94 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Mitsuteru Yukishita, Akira Nagoya, Yasufumi Itoh, and Shinji Kimura: "Hardware/Software Co-design System (in Japanese)" Technical Report of IPSJ. DA78-21. 127-132 (1995)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Shinji Kimura, Makoto Hirao, Kazuyoshi Takagi and Katsumasa Watanabe: "Timing Analysis of Logic Circuits with Multiple Clock Operations" Technical Report of IEICE. VLD96-33. 53-58 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Yasufumi Itoh, Makoto Hirao, Shinji Kimura and Katsumasa Watanabe: "Hardware/Software Codesign Compiler for General Purpose Coprocessor GPCP-SS (in Japanese)" Proceedings of DA Symposium'96. 123-128 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Takanori Sakate, Shinji Kimura and Katsumasa Watanabe: "A Reduaction Method of Register Transfer Level Logic Circuits for Design Verification (in Japanese)" Technical Report of IEICE. VLD96-91. (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Yasufumi Itoh, Makoto Hirao, Kazuyoshi Takagi, Shinji Kimura and Katsumasa Watanabe: "Hardware/Software Codesign and Co-operation on General Purpose Coprocessor using DMA (in Japanese)" Technical Report of IEICE. VLD96-98 ICD96-208. 17-22 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] S.Kimura, M.Yukishita, Y.Itoh, A.Nagoya, M.Hirao and K.Watanabe: "A Hardware/Software Codesign Method for a General Purpose Reconfigurable Coprocessor" 5th International Workshop on Hardware/Software Codesign (CODES/CASHE'97). 147-151 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Yasufumi Itoh, Shinji Kimura, and Katsumasa Watanabe: "Hardware Resource Management on Computer Systems with Reconfigurable Hardware (in Japanese)" Technical Report of IEICE. VLD97-101. 9-14 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Kazuhiro Nakamura, Shinji Kimura, Kazuyoshi Takagi and Katsumasa Watanabe: "Waiting False Path Analysis of Sequential Logic Circuits (in Japanese)" Technical Report of IEICE. VLD97-133. 71-78 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] 伊藤康史, 木村晋二, 渡邉勝正: "可変ハードウェアを有する計算機システムにおけるハードウェア資源の管理について" 電子情報通信学会 VLD研究会. VLD97-101(CPSY97-89). 9-14 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] 中村一博, 木村晋二, 高木一義, 渡邉勝正: "順序回路の待ち状態に起因するフォールスパスの解析手法" 電子情報通信学会 VLD研究会. (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] 中村一博, 木村晋二, 高木一義, 渡邉勝正: "順序回路の待ち状態に起因するフォールスパスの解析とそれを用いたタイミング検証" 電子情報通信学会 総合大会. A-3-8. (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] 木村晋二、平尾誠、高木一義、渡邉勝正: "マルチクロック演算を考慮した論理回路のタイミング解析" 電子情報通信学会VLD研究会. VLD96-33 No.201. 53-58 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] 伊藤康史、平尾誠、木村晋二、渡邉勝正: "汎用コプロセッサGPCP-SSのハードウェア/ソフトウェア協調設計のためのコンパイラ" 情報処理学会DAシンポジウム'96論文集. 123-128 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] 伊藤康史、平尾誠、高木一義、木村晋二、渡邉勝正: "汎用コプロセッサを有する計算機システムのためのハードウェア/ソフトウェア協調設計手法" 電子情報通信学会ソサイエティ大会講演論文集. A-66. (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] 平尾誠、伊藤康史、高木一義、木村晋二、渡邉勝正: "汎用コプロセッサのための最大遅延を保証するハードウェア設計手法の提案" 電子情報通信学会ソサイエティ大会講演論文集. A-67. (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] 伊藤康史、平尾誠、高木一義、木村晋二、渡邉勝正: "汎用コプロセッサのDNAを用いたハードウェア/ソフトウェア協調動作法およびそのハードウェア部の最適化法について" 電子情報通信学会ICD研究会/VLD研究会. VLD96-98(ICD96-208)No.556. 17-22 (1997)

    • Related Report
      1996 Annual Research Report
  • [Publications] Shinji Kimura,Mitsuteru Yukishita,Yasufumi Itoh,Akira Nagoya,Makoto Hirao,Katsumasa Watanabe: "A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Rrocessor" Proceedings of 5th IEEE International Workshop on Hardware/Software Codesign. (1997)

    • Related Report
      1996 Annual Research Report
  • [Publications] 伊藤,康史: "汎用コプロセッサGPCP-SSの実現と評価" 信学技報VLD95-100. 87-94 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] 雪下,充輝: "ハードウェア/ソフトウェア協調設計システム" 情報研報DA 78-21. 127-132 (1995)

    • Related Report
      1995 Annual Research Report

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Published: 1995-04-01   Modified: 2016-04-21  

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