| Project/Area Number |
07555117
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 試験 |
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| Research Field |
情報通信工学
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| Research Institution | The University of Tokyo |
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Principal Investigator |
AIZAWA Kiyoharu Univ. of Tokyo Department of Information and Communication Eng., Associate Profassor, 大学院・工学系研究科, 助教授 (20192453)
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| Co-Investigator(Kenkyū-buntansha) |
HATORI Mitsutoshi Univ. of Tokyo Department of Information and Communication Eng., Profassor, 大学院・工学系研究科, 教授 (60010790)
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| Project Period (FY) |
1995 – 1996
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| Project Status |
Completed (Fiscal Year 1996)
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| Budget Amount *help |
¥7,500,000 (Direct Cost: ¥7,500,000)
Fiscal Year 1996: ¥2,800,000 (Direct Cost: ¥2,800,000)
Fiscal Year 1995: ¥4,700,000 (Direct Cost: ¥4,700,000)
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| Keywords | Image Sensor / Intelligent Sensor / Image compression / Smart Sensor / Computational Sensor / CMOS Sensor |
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| Research Abstract |
In this research, we propose a novel image sensor on which image signal can be compressed Since image single is compressed on the imager plane by making use of parallel nature of image signals, the amount of sigual read out from the imager can be significantly reduced. Thus, the proposed sensor can be potentially applied to high pixel rate cameras and processing systems which require very high speed imaging and very high resolution for real time imaging ; the very high bandwidth is the fundamental limitation for feasibility of those high pixel rate sensors and processing systems.
Conditional replenishment algorithm is employed for the compression scheme ; it detects temporally changing pixels as active pixels and output those active pixels. Two architechtures of compression sensors listed below were investigated. The prototypes based on both approaches operate more than 1000 frames per second.
(1) Pixel Parallel Architecture
All the required computational elements, that are detection, rate control and address encoding, were implemented. A prototype VLSI which has 32 x 32 pixels was examined.
(2) Column Parallel Architecture
In order to improve fill factor and power dissipation, a column parallel architecture were investigated. A prototype VLSI which has 32 x 32 pixels was implemented and shows good quality of pitures.
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